clean verilator lint by making parameters integer (instead of being inferred as real)

2024-05-24 22:43:34 +08:00 · 2024-05-24 22:43:34 +08:00 · 18283f4436
parent 88a913f8da
commit 18283f4436
1 changed files with 1 additions and 1 deletions
--- a/rtl/ddr3_controller.v
+++ b/rtl/ddr3_controller.v
@ -36,7 +36,7 @@
 //`define RAM_8Gb

 module ddr3_controller #(
-    parameter      CONTROLLER_CLK_PERIOD = 10_000, //ps, clock period of the controller interface
+    parameter integer CONTROLLER_CLK_PERIOD = 10_000, //ps, clock period of the controller interface
                   DDR3_CLK_PERIOD = 2_500, //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD) 
                   ROW_BITS = 14,   //width of DDR3 row address
                   COL_BITS = 10, //width of DDR3 column address