AngeloJacobo
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83b7b95af4
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pass verilator warning
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2023-08-20 12:32:51 +08:00 |
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AngeloJacobo
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a8aec13ed9
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using different address now finally works!
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2023-08-20 11:52:54 +08:00 |
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AngeloJacobo
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00757338da
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update wcfg
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2023-08-20 11:21:16 +08:00 |
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AngeloJacobo
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5df83b8182
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added working bitfiles for arty s7
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2023-08-20 11:20:41 +08:00 |
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AngeloJacobo
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989e8dd9e7
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use macro for defining the ddr3 config (EIGHT_LANES_x8 or TWO_LANES_x8) and the source of clk (if clock wizard or not)
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2023-08-20 11:13:50 +08:00 |
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AngeloJacobo
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7c68bee5e8
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changed for x8 config
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2023-08-20 11:10:15 +08:00 |
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AngeloJacobo
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e2653d5793
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reset for IO is released only after IDELAYCTRL is ready, added also IODELAY_GROUP
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2023-08-20 11:09:38 +08:00 |
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AngeloJacobo
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9769a7cfaa
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pass formal for 8-lane config and pass verilator linting
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2023-08-20 11:07:22 +08:00 |
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AngeloJacobo
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e839e220c3
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ddr3 model fails when ROW_BITS less than 16 (has Z value in address)
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2023-08-17 11:42:09 +08:00 |
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AngeloJacobo
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ef8b1b84fc
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update wcfg
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2023-08-17 11:41:05 +08:00 |
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AngeloJacobo
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c97e5a8c1f
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added test for testing design in ARTY-S7
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2023-08-17 11:40:41 +08:00 |
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AngeloJacobo
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c9b19ac887
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added uart submodule
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2023-08-17 11:36:15 +08:00 |
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AngeloJacobo
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36c93689e5
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redo read/write calibration if data read is wrong
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2023-08-17 11:27:23 +08:00 |
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AngeloJacobo
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a8bf429bc8
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allow tdqs off and use dm
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2023-08-15 21:17:13 +08:00 |
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AngeloJacobo
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f296d08c6b
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add option for ODELAY_SUPPORTED=0 and added port for i_ddr3_clk_90
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2023-08-15 19:37:28 +08:00 |
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AngeloJacobo
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411febc1a8
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add option for ODELAY_SUPPORTED=0 (for FPGAs without ODELAY)
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2023-08-15 19:35:44 +08:00 |
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AngeloJacobo
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b3ab21a6d5
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add option for ODELAY_SUPPORTED=0 (for FPGAs without ODELAY)
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2023-08-15 19:12:49 +08:00 |
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Angelo Jacobo
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b762c464f6
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add images for hardware debug
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2023-08-04 19:18:47 +08:00 |
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AngeloJacobo
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a7ebaefbdb
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add autofpga text file for wbscope
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2023-08-04 18:57:03 +08:00 |
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AngeloJacobo
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80f12d1663
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move to kintex_switch_files folder
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2023-08-04 16:37:48 +08:00 |
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AngeloJacobo
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69768da1c8
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added files for kintex switch project (autofpga files, xdc, wbscope cpp)
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2023-08-04 16:37:10 +08:00 |
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AngeloJacobo
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e9f1ab4971
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modify debug port logic for wbscope
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2023-08-04 07:57:09 +08:00 |
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AngeloJacobo
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bc66655ca7
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just fixed delay
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2023-08-04 07:54:20 +08:00 |
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AngeloJacobo
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0753e6e157
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fixed localparam value for wb_addr_bits
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2023-08-04 07:53:12 +08:00 |
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AngeloJacobo
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72dc00742b
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correct generate indexes
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2023-08-04 07:52:31 +08:00 |
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AngeloJacobo
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1bfd851a6e
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pass formal with LANES either 1,2,4,8
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2023-08-04 07:49:25 +08:00 |
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AngeloJacobo
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7c76a15087
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update wcfg
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2023-08-01 15:59:34 +08:00 |
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AngeloJacobo
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2c73f38f99
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added debug port and max function for int type
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2023-08-01 15:58:58 +08:00 |
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AngeloJacobo
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e4bd0ac09c
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delete|
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2023-07-24 19:46:23 +08:00 |
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AngeloJacobo
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92dcb0990a
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update gitignore
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2023-07-24 17:37:07 +08:00 |
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AngeloJacobo
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d2ae29c26a
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simulation file for SODIMM
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2023-07-24 17:34:40 +08:00 |
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AngeloJacobo
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4589fc3dfe
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script for running verilator, yosys, iverilog, and then symbiyosys
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2023-07-24 17:33:56 +08:00 |
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AngeloJacobo
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4e5b98f485
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use SODIMM instead of DIMM in simulation
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2023-07-24 17:32:56 +08:00 |
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AngeloJacobo
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da10a5f5d1
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Merge branch 'main' of https://github.com/AngeloJacobo/DDR3_Controller into main
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2023-07-24 17:30:45 +08:00 |
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AngeloJacobo
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d5f1d600ea
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resolve verilator warnings and add option YOSYS for not using input real in functions
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2023-07-24 17:27:17 +08:00 |
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AngeloJacobo
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47ba90962a
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delete this later
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2023-07-23 10:16:19 +08:00 |
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Angelo Jacobo
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1c5e9213b0
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Update README.md
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2023-07-20 18:47:32 +08:00 |
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Angelo Jacobo
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1f57ee841e
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Update README.md
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2023-07-20 18:31:03 +08:00 |
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AngeloJacobo
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234c587229
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working txt for autofpga
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2023-07-19 18:58:51 +08:00 |
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AngeloJacobo
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5486aa4429
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removed old
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2023-07-19 18:58:31 +08:00 |
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AngeloJacobo
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487b026f6c
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add test to wb2
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2023-07-19 18:50:23 +08:00 |
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AngeloJacobo
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c885e3286c
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update wcfg
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2023-07-19 18:48:59 +08:00 |
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AngeloJacobo
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60e40f9d35
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less simulation warning
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2023-07-19 18:48:31 +08:00 |
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AngeloJacobo
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e38859ef78
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resolved warning from vivado on IOBDELAY
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2023-07-19 18:47:24 +08:00 |
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AngeloJacobo
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7142dd9cdb
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added more registers and formal assertions to wb2
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2023-07-19 18:46:36 +08:00 |
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AngeloJacobo
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137e30ba36
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resolve vivado warnings
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2023-07-17 21:39:07 +08:00 |
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AngeloJacobo
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97e740139f
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resolved vivado warnings
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2023-07-17 21:38:20 +08:00 |
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AngeloJacobo
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983919d9df
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removed unneeded .* files
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2023-07-16 08:52:10 +08:00 |
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AngeloJacobo
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12c947afb1
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Merge branch 'main' of https://github.com/AngeloJacobo/DDR3_Controller into main
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2023-07-16 08:46:27 +08:00 |
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AngeloJacobo
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4f857e08f4
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add files back after git rm -r cached .
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2023-07-16 08:46:16 +08:00 |