move to kintex_switch_files folder
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AngeloJacobo
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351
ddr3.txt
351
ddr3.txt
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################################################################################
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##
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## Filename: ddr3.txt
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## {{{
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## Project: 10Gb Ethernet switch
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##
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## Purpose: To describe how to provide access to an SDRAM controller
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## from the Wishbone bus, where such SDRAM controller uses a
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## different clock from the Wishbone bus itself.
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##
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## Creator: Dan Gisselquist, Ph.D.
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## Gisselquist Technology, LLC
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##
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################################################################################
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## }}}
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## Copyright (C) 2023, Gisselquist Technology, LLC
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## {{{
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## This file is part of the ETH10G project.
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##
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## The ETH10G project contains free software and gateware, licensed under the
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## Apache License, Version 2.0 (the "License"). You may not use this project,
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## or this file, except in compliance with the License. You may obtain a copy
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## of the License at
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## }}}
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## http://www.apache.org/licenses/LICENSE-2.0
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## {{{
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## Unless required by applicable law or agreed to in writing, files
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## distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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## WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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## License for the specific language governing permissions and limitations
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## under the License.
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##
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################################################################################
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##
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## }}}
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# Wishbone 1
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@PREFIX=ddr3_controller
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@DEVID=DDR3_CONTROLLER
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@ACCESS=@$(DEVID)_ACCESS
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## LGMEMSZ is the size of the SDRAM in bytes, 29 => 512MB
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@$LGMEMSZ=29
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@LGMEMSZ.FORMAT=%d
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## UNUSED = log_2(512) = 9
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@$UNUSED=9
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@$NADDR=(1<<(LGMEMSZ-(@$(UNUSED))))
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@$NBYTES=(1<<(@$LGMEMSZ))
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@NBYTES.FORMAT=0x%08x
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@$MADDR= @$(REGBASE)
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@MADDR.FORMAT=0x%08x
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@SLAVE.TYPE=MEMORY
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@SLAVE.BUS=wbwide
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@BUS=wbwide
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# 8-bit byte accesses
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@$ABITS=@$(LGMEMSZ)-@$(UNUSED)
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@LD.PERM=wx
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#
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@REGS.N=1
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@REGS.0= 0 R_@$(DEVID) @$(DEVID)
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@REGDEFS.H.DEFNS=
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#define @$(DEVID)BASE @$[0x%08x](REGBASE)
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@BDEF.OSDEF=_BOARD_HAS_@$(DEVID)
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@BDEF.OSVAL=extern char _@$(PREFIX)[@$NBYTES];
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@TOP.PORTLIST=
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// DDR3 I/O port wires
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o_ddr3_reset_n, o_ddr3_cke, o_ddr3_clk_p, o_ddr3_clk_n,
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o_ddr3_s_n, o_ddr3_ras_n, o_ddr3_cas_n, o_ddr3_we_n,
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o_ddr3_ba, o_ddr3_a,
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o_ddr3_odt, o_ddr3_dm,
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io_ddr3_dqs_p, io_ddr3_dqs_n, io_ddr3_dq
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@TOP.PARAM=
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localparam real CONTROLLER_CLK_PERIOD = 10, //ns, period of clock input to this DDR3 controller module
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DDR3_CLK_PERIOD = 2.5; //ns, period of clock input to DDR3 RAM device
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localparam ROW_BITS = 14, //width of row address
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BA_BITS = 3, //width of bank address
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DQ_BITS = 8, //width of DQ
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LANES = 8; //8 lanes of DQ
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localparam serdes_ratio = $rtoi(CONTROLLER_CLK_PERIOD/DDR3_CLK_PERIOD),
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wb_data_bits = DQ_BITS*LANES*serdes_ratio*2,
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wb_sel_bits = wb_data_bits / 8,
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//4 is the width of a single ddr3 command {cs_n, ras_n, cas_n, we_n} plus 3 (ck_en, odt, reset_n) plus bank bits plus row bits
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cmd_len = 4 + 3 + BA_BITS + ROW_BITS;
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@TOP.IODECL=
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// I/O declarations for the DDR3 SDRAM
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// {{{
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output wire o_ddr3_reset_n;
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output wire [1:0] o_ddr3_cke;
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output wire [0:0] o_ddr3_clk_p, o_ddr3_clk_n;
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output wire [1:0] o_ddr3_s_n; // o_ddr3_s_n[1] is set to 0 since controller only support single rank
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output wire [0:0] o_ddr3_ras_n, o_ddr3_cas_n, o_ddr3_we_n;
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output wire [BA_BITS-1:0] o_ddr3_ba;
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output wire [15:0] o_ddr3_a; //set to max of 16 bits, but only ROW_BITS bits are relevant
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output wire [1:0] o_ddr3_odt;
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output wire [LANES-1:0] o_ddr3_dm;
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inout wire [(DQ_BITS*LANES)/8-1:0] io_ddr3_dqs_p, io_ddr3_dqs_n;
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inout wire [(DQ_BITS*LANES)-1:0] io_ddr3_dq;
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// }}}
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@TOP.DEFNS=
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// Wires connected to PHY interface of DDR3 controller
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// {{{
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wire [DQ_BITS*LANES*8-1:0] @$(PREFIX)_iserdes_data;
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wire [LANES*8-1:0] @$(PREFIX)_iserdes_dqs;
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wire [LANES*8-1:0] @$(PREFIX)_iserdes_bitslip_reference;
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wire @$(PREFIX)_idelayctrl_rdy;
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wire [cmd_len*serdes_ratio-1:0] @$(PREFIX)_cmd;
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wire @$(PREFIX)_dqs_tri_control, @$(PREFIX)_dq_tri_control;
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wire @$(PREFIX)_toggle_dqs;
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wire [wb_data_bits-1:0] @$(PREFIX)_data;
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wire [wb_sel_bits-1:0] @$(PREFIX)_dm;
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wire [4:0] @$(PREFIX)_odelay_data_cntvaluein, @$(PREFIX)_odelay_dqs_cntvaluein;
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wire [4:0] @$(PREFIX)_idelay_data_cntvaluein, @$(PREFIX)_idelay_dqs_cntvaluein;
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wire [LANES-1:0] @$(PREFIX)_odelay_data_ld, @$(PREFIX)_odelay_dqs_ld;
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wire [LANES-1:0] @$(PREFIX)_idelay_data_ld, @$(PREFIX)_idelay_dqs_ld;
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wire [LANES-1:0] @$(PREFIX)_bitslip;
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// }}}
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@TOP.MAIN=
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// DDR3 Controller-PHY Interface
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@$(PREFIX)_iserdes_data, @$(PREFIX)_iserdes_dqs,
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@$(PREFIX)_iserdes_bitslip_reference,
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@$(PREFIX)_idelayctrl_rdy,
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@$(PREFIX)_cmd,
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@$(PREFIX)_dqs_tri_control, @$(PREFIX)_dq_tri_control,
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@$(PREFIX)_toggle_dqs, @$(PREFIX)_data, @$(PREFIX)_dm,
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@$(PREFIX)_odelay_data_cntvaluein, @$(PREFIX)_odelay_dqs_cntvaluein,
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@$(PREFIX)_idelay_data_cntvaluein, @$(PREFIX)_idelay_dqs_cntvaluein,
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@$(PREFIX)_odelay_data_ld, @$(PREFIX)_odelay_dqs_ld,
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@$(PREFIX)_idelay_data_ld, @$(PREFIX)_idelay_dqs_ld,
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@$(PREFIX)_bitslip
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@TOP.INSERT=
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// DDR3 PHY Instantiation
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ddr3_phy #(
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.ROW_BITS(ROW_BITS), //width of row address
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.BA_BITS(BA_BITS), //width of bank address
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.DQ_BITS(DQ_BITS), //width of DQ
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.LANES(LANES), //8 lanes of DQ
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.CONTROLLER_CLK_PERIOD(CONTROLLER_CLK_PERIOD), //ns, period of clock input to this DDR3 controller module
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.DDR3_CLK_PERIOD(DDR3_CLK_PERIOD) //ns, period of clock input to DDR3 RAM device
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) ddr3_phy_inst (
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// clock and reset
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.i_controller_clk(s_clk),
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.i_ddr3_clk(s_clk4x),
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.i_ref_clk(s_clk200),
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.i_rst_n(!s_reset),
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// Controller Interface
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.i_controller_cmd(@$(PREFIX)_cmd),
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.i_controller_dqs_tri_control(@$(PREFIX)_dqs_tri_control),
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.i_controller_dq_tri_control(@$(PREFIX)_dq_tri_control),
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.i_controller_toggle_dqs(@$(PREFIX)_toggle_dqs),
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.i_controller_data(@$(PREFIX)_data),
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.i_controller_dm(@$(PREFIX)_dm),
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.i_controller_odelay_data_cntvaluein(@$(PREFIX)_odelay_data_cntvaluein),
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.i_controller_odelay_dqs_cntvaluein(@$(PREFIX)_odelay_dqs_cntvaluein),
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.i_controller_idelay_data_cntvaluein(@$(PREFIX)_idelay_data_cntvaluein),
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.i_controller_idelay_dqs_cntvaluein(@$(PREFIX)_idelay_dqs_cntvaluein),
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.i_controller_odelay_data_ld(@$(PREFIX)_odelay_data_ld),
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.i_controller_odelay_dqs_ld(@$(PREFIX)_odelay_dqs_ld),
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.i_controller_idelay_data_ld(@$(PREFIX)_idelay_data_ld),
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.i_controller_idelay_dqs_ld(@$(PREFIX)_idelay_dqs_ld),
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.i_controller_bitslip(@$(PREFIX)_bitslip),
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.o_controller_iserdes_data(@$(PREFIX)_iserdes_data),
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.o_controller_iserdes_dqs(@$(PREFIX)_iserdes_dqs),
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.o_controller_iserdes_bitslip_reference(@$(PREFIX)_iserdes_bitslip_reference),
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.o_controller_idelayctrl_rdy(@$(PREFIX)_idelayctrl_rdy),
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// DDR3 I/O Interface
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.o_ddr3_clk_p(o_ddr3_clk_p),
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.o_ddr3_clk_n(o_ddr3_clk_n),
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.o_ddr3_reset_n(o_ddr3_reset_n),
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.o_ddr3_cke(o_ddr3_cke[0]), // CKE
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.o_ddr3_cs_n(o_ddr3_s_n[0]), // chip select signal (controls rank 1 only)
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.o_ddr3_ras_n(o_ddr3_ras_n), // RAS#
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.o_ddr3_cas_n(o_ddr3_cas_n), // CAS#
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.o_ddr3_we_n(o_ddr3_we_n), // WE#
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.o_ddr3_addr(o_ddr3_a[ROW_BITS-1:0]),
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.o_ddr3_ba_addr(o_ddr3_ba),
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.io_ddr3_dq(io_ddr3_dq),
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.io_ddr3_dqs(io_ddr3_dqs_p),
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.io_ddr3_dqs_n(io_ddr3_dqs_n),
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.o_ddr3_dm(o_ddr3_dm),
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.o_ddr3_odt(o_ddr3_odt[0]) // on-die termination
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);
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assign o_ddr3_s_n[1] = 1; // set to 1 (disabled) since controller only supports single rank
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assign o_ddr3_cke[1] = 0; // set to 0 (disabled) since controller only supports single rank
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assign o_ddr3_odt[1] = 0; // set to 0 (disabled) since controller only supports single rank
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genvar gen_index;
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generate
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for(gen_index = ROW_BITS; gen_index < 16; gen_index = gen_index + 1) begin
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assign o_ddr3_a[gen_index] = 0;
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end
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endgenerate
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@MAIN.PORTLIST=
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// DDR3 Controller Interface
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i_@$(PREFIX)_iserdes_data, i_@$(PREFIX)_iserdes_dqs,
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i_@$(PREFIX)_iserdes_bitslip_reference,
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i_@$(PREFIX)_idelayctrl_rdy,
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o_@$(PREFIX)_cmd,
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o_@$(PREFIX)_dqs_tri_control, o_@$(PREFIX)_dq_tri_control,
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o_@$(PREFIX)_toggle_dqs, o_@$(PREFIX)_data, o_@$(PREFIX)_dm,
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o_@$(PREFIX)_odelay_data_cntvaluein, o_@$(PREFIX)_odelay_dqs_cntvaluein,
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o_@$(PREFIX)_idelay_data_cntvaluein, o_@$(PREFIX)_idelay_dqs_cntvaluein,
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o_@$(PREFIX)_odelay_data_ld, o_@$(PREFIX)_odelay_dqs_ld,
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o_@$(PREFIX)_idelay_data_ld, o_@$(PREFIX)_idelay_dqs_ld,
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o_@$(PREFIX)_bitslip
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@MAIN.PARAM=
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localparam real CONTROLLER_CLK_PERIOD = 10, //ns, period of clock input to this DDR3 controller module
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DDR3_CLK_PERIOD = 2.5; //ns, period of clock input to DDR3 RAM device
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localparam ROW_BITS = 14, //width of row address
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COL_BITS = 10, //width of column address
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BA_BITS = 3, //width of bank address
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DQ_BITS = 8, //width of DQ
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LANES = 8, //8 lanes of DQ
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AUX_WIDTH = 16;
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localparam serdes_ratio = $rtoi(CONTROLLER_CLK_PERIOD/DDR3_CLK_PERIOD),
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wb_data_bits = DQ_BITS*LANES*serdes_ratio*2,
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wb_sel_bits = wb_data_bits / 8,
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//4 is the width of a single ddr3 command {cs_n, ras_n, cas_n, we_n} plus 3 (ck_en, odt, reset_n) plus bank bits plus row bits
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cmd_len = 4 + 3 + BA_BITS + ROW_BITS;
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@MAIN.IODECL=
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// DDR3 Controller I/O declarations
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// {{{
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input wire [DQ_BITS*LANES*8-1:0] i_@$(PREFIX)_iserdes_data;
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input wire [LANES*8-1:0] i_@$(PREFIX)_iserdes_dqs;
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input wire [LANES*8-1:0] i_@$(PREFIX)_iserdes_bitslip_reference;
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input wire i_@$(PREFIX)_idelayctrl_rdy;
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output wire [cmd_len*serdes_ratio-1:0] o_@$(PREFIX)_cmd;
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output wire o_@$(PREFIX)_dqs_tri_control, o_@$(PREFIX)_dq_tri_control;
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output wire o_@$(PREFIX)_toggle_dqs;
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output wire [wb_data_bits-1:0] o_@$(PREFIX)_data;
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output wire [wb_sel_bits-1:0] o_@$(PREFIX)_dm;
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output wire [4:0] o_@$(PREFIX)_odelay_data_cntvaluein, o_@$(PREFIX)_odelay_dqs_cntvaluein;
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output wire [4:0] o_@$(PREFIX)_idelay_data_cntvaluein, o_@$(PREFIX)_idelay_dqs_cntvaluein;
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output wire [LANES-1:0] o_@$(PREFIX)_odelay_data_ld, o_@$(PREFIX)_odelay_dqs_ld;
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output wire [LANES-1:0] o_@$(PREFIX)_idelay_data_ld, o_@$(PREFIX)_idelay_dqs_ld;
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output wire [LANES-1:0] o_@$(PREFIX)_bitslip;
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// }}}
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@MAIN.INSERT=
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////////////////////////////////////////////////////////////////////////
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//
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// DDR3 Controller instantiation
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// {{{
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ddr3_controller #(
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.CONTROLLER_CLK_PERIOD(CONTROLLER_CLK_PERIOD), //ns, period of clock input to this DDR3 controller module
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.DDR3_CLK_PERIOD(DDR3_CLK_PERIOD), //ns, period of clock input to DDR3 RAM device
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.ROW_BITS(ROW_BITS), //width of row address
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.COL_BITS(COL_BITS), //width of column address
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.BA_BITS(BA_BITS), //width of bank address
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.DQ_BITS(DQ_BITS), //width of DQ
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.LANES(LANES), //8 lanes of DQ
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.AUX_WIDTH(AUX_WIDTH), //
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.OPT_LOWPOWER(1), //1 = low power, 0 = low logic
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.OPT_BUS_ABORT(1) //1 = can abort bus, 0 = no abort (i_wb_cyc will be ignored, ideal for an AXI implementation which cannot abort transaction)
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) ddr3_controller_inst (
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.i_controller_clk(i_clk), //i_controller_clk has period of CONTROLLER_CLK_PERIOD
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.i_rst_n(!i_reset), //200MHz input clock
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// Wishbone 1 (Controller)
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@$(SLAVE.ANSIPORTLIST),
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.i_aux(0),
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.o_aux(),
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// Wishbone 2 (PHY)
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@$(ddr3_phy.SLAVE.ANSIPORTLIST),
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//
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// PHY interface
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.i_phy_iserdes_data(i_@$(PREFIX)_iserdes_data),
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.i_phy_iserdes_dqs(i_@$(PREFIX)_iserdes_dqs),
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.i_phy_iserdes_bitslip_reference(i_@$(PREFIX)_iserdes_bitslip_reference),
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.i_phy_idelayctrl_rdy(i_@$(PREFIX)_idelayctrl_rdy),
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.o_phy_cmd(o_@$(PREFIX)_cmd),
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.o_phy_dqs_tri_control(o_@$(PREFIX)_dqs_tri_control),
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.o_phy_dq_tri_control(o_@$(PREFIX)_dq_tri_control),
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.o_phy_toggle_dqs(o_@$(PREFIX)_toggle_dqs),
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.o_phy_data(o_@$(PREFIX)_data),
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.o_phy_dm(o_@$(PREFIX)_dm),
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.o_phy_odelay_data_cntvaluein(o_@$(PREFIX)_odelay_data_cntvaluein),
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.o_phy_odelay_dqs_cntvaluein(o_@$(PREFIX)_odelay_dqs_cntvaluein),
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.o_phy_idelay_data_cntvaluein(o_@$(PREFIX)_idelay_data_cntvaluein),
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.o_phy_idelay_dqs_cntvaluein(o_@$(PREFIX)_idelay_dqs_cntvaluein),
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.o_phy_odelay_data_ld(o_@$(PREFIX)_odelay_data_ld),
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.o_phy_odelay_dqs_ld(o_@$(PREFIX)_odelay_dqs_ld),
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.o_phy_idelay_data_ld(o_@$(PREFIX)_idelay_data_ld),
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.o_phy_idelay_dqs_ld(o_@$(PREFIX)_idelay_dqs_ld),
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.o_phy_bitslip(o_@$(PREFIX)_bitslip)
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);
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// }}}
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#
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@PREFIX=ddr3_phy
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@DEVID=DDR3_PHY
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@ACCESS=@$(DEVID)_ACCESS
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@$NADDR=1024
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@SLAVE.TYPE=MEMORY
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@SLAVE.BUS=wb32
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@SLAVE.ANSPREFIX=wb2_
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# 8-bit byte accesses
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@LD.PERM=wx
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#
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@REGS.N=1
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@REGS.0= 0 R_@$(DEVID) @$(DEVID)
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@REGDEFS.H.DEFNS=
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#define @$(DEVID)BASE @$[0x%08x](REGBASE)
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@BDEF.OSDEF=_BOARD_HAS_@$(DEVID)
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@BDEF.OSVAL=extern char _@$(PREFIX)[@$NBYTES];
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@SIM.INCLUDE=
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#include "memsim.h"
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@SIM.DEFNS=
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#ifdef @$(ACCESS)
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MEMSIM *m_@$(PREFIX);
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#endif // @$(ACCESS)
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@SIM.INIT=
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#ifdef @$(ACCESS)
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m_@$(PREFIX) = new MEMSIM(@$(NBYTES));
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#endif // @$(ACCESS)
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@SIM.CLOCK=@$(SLAVE.BUS.CLOCK.NAME)
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@SIM.TICK=
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#ifdef @$(ACCESS)
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// Simulate the SDRAM
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// {{{
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(*m_@$(PREFIX))(m_core->o_@$(PREFIX)_cyc,
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m_core->o_@$(PREFIX)_stb,
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m_core->o_@$(PREFIX)_we,
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m_core->o_@$(PREFIX)_addr,
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&m_core->o_@$(PREFIX)_data,
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m_core->o_@$(PREFIX)_sel,
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m_core->i_@$(PREFIX)_stall,
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m_core->i_@$(PREFIX)_ack,
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&m_core->i_@$(PREFIX)_data);
|
||||
m_core->i_@$(PREFIX)_err = 0;
|
||||
// }}}
|
||||
#endif // @$(ACCESS)
|
||||
@SIM.LOAD=
|
||||
m_@$(PREFIX)->load(start, &buf[offset], wlen);
|
||||
|
||||
Loading…
Reference in New Issue