AngeloJacobo
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157cca28d8
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fixed late_dq logic
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2025-05-12 18:27:57 +08:00 |
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AngeloJacobo
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90647a70e0
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resolved (again) the verilator lint
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2025-05-12 16:28:07 +08:00 |
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AngeloJacobo
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50c0a6488d
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verilator now passing lint even with older verilator version
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2025-05-11 20:02:13 +08:00 |
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AngeloJacobo
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b990372663
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added support for DLL_OFF and Lattice ECP5 PHY
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2025-04-19 13:24:20 +08:00 |
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AngeloJacobo
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c0bc4ca48a
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removed extra semicolon
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2025-03-02 18:46:07 +08:00 |
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AngeloJacobo
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94b4e0866b
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added UART for debugging, DQ now support 1 cycle late
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2025-03-02 14:15:44 +08:00 |
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AngeloJacobo
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5c52351bce
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uncommented default_nettype
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2025-03-01 19:32:35 +08:00 |
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AngeloJacobo
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e19c6023c4
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remove wb2 related logic when SECOND_WISHBONE == 0 to pass DDR3-1600 timing
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2025-03-01 15:51:48 +08:00 |
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AngeloJacobo
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74f68760a4
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removed mark_debug
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2025-03-01 14:40:21 +08:00 |
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Angelo Jacobo
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3898b1e762
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Merge branch 'main' into higher_speed_feature
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2025-02-22 11:31:54 +08:00 |
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AngeloJacobo
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d4ecfee105
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improve latency of ack after write
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2025-02-09 16:16:42 +08:00 |
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AngeloJacobo
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7ada4bcbab
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add support for BIST_MODE = 0,1,and 2 , write data is also randomized
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2025-02-09 09:48:46 +08:00 |
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AngeloJacobo
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c81f9044d8
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add activate-to-activate delay, calibrate-able for both late-write-dq and early-read-dq, simulation passing for ddr3-1600!
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2025-01-30 19:07:09 +08:00 |
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AngeloJacobo
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760979db27
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hardware runs on ddr3-1333! Now working on ddr3-1600
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2025-01-19 17:15:40 +08:00 |
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AngeloJacobo
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d8cb6d16d9
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update copyright date
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2025-01-02 13:18:42 +08:00 |
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AngeloJacobo
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f636dcbd2e
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bring all timing parameters to top
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2024-12-29 21:22:52 +08:00 |
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AngeloJacobo
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3b2ef2afa8
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odt[1] generated by separate oserdes to make it routable
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2024-12-21 18:24:12 +08:00 |
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AngeloJacobo
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7367182640
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dual rank enabled is now passing formal and simulation!
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2024-12-20 18:56:21 +08:00 |
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AngeloJacobo
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4fdaace899
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add dual-rank feature (PHY ongoing changes)
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2024-12-02 11:28:21 +08:00 |
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AngeloJacobo
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05589c3f83
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added self-refresh to vivado IP GUI, tested self-refresh on hardware with microblaze
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2024-11-24 17:40:21 +08:00 |
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AngeloJacobo
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e08612658b
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self-refresh feature done, passing simulation and formal
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2024-11-24 14:31:20 +08:00 |
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AngeloJacobo
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1078e2ffe0
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Revert "add self-refresh option, passing Simulation, ongoing formal"
This reverts commit a5e2adf4a4.
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2024-11-23 11:43:05 +08:00 |
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AngeloJacobo
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a5e2adf4a4
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add self-refresh option, passing Simulation, ongoing formal
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2024-11-17 20:47:14 +08:00 |
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AngeloJacobo
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c58a9d70e6
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add self-refresh feature (untested)
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2024-11-03 14:52:32 +08:00 |
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AngeloJacobo
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65bcf2f621
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add option to skip internal test for Microblaze use
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2024-10-26 09:07:24 +08:00 |
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Angelo Jacobo
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aa68c22169
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turn off ECC test by default
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2024-09-01 09:04:45 +08:00 |
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AngeloJacobo
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fc963c3c23
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simulation and formal are now passing for all ECC types
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2024-07-28 17:36:37 +08:00 |
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AngeloJacobo
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f80d4ac21b
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simulation passing for ECC_ENABLE = 3
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2024-07-15 18:31:49 +08:00 |
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AngeloJacobo
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de85925681
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add support for ECC_ENABLE = 3
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2024-07-06 21:24:01 +08:00 |
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AngeloJacobo
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71b0383cda
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add support for other memory address mapping (row_bank_col = 0,1, or 2)
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2024-07-06 09:01:34 +08:00 |
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AngeloJacobo
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c81c51c9f4
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add support for ECC = 1 and 2, passing simulation and formal verification
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2024-06-29 19:36:01 +08:00 |
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AngeloJacobo
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7d93717b72
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add initial ECC, ECC_ENABLE = 2 working
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2024-06-17 16:25:06 +08:00 |
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AngeloJacobo
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8fb24dd180
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add copyright on headers
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2024-06-09 12:01:30 +08:00 |
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AngeloJacobo
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a1b15fb9d6
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elevate DIC and RTT_NOM as parameters
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2024-06-09 10:50:18 +08:00 |
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AngeloJacobo
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9c440d535f
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fix bug in write levelling with cntvalue > 15 (reaches 31), changed mark_debug for debugging
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2024-06-02 19:19:17 +08:00 |
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AngeloJacobo
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a6982da97d
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match dic and rtt_nom settings
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2024-05-26 20:53:00 +08:00 |
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AngeloJacobo
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eaa45f01d5
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fix error in formal verif
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2024-05-26 20:27:53 +08:00 |
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AngeloJacobo
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57aebc6eef
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fixed error in slot calculation
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2024-05-25 13:49:48 +08:00 |
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AngeloJacobo
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18283f4436
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clean verilator lint by making parameters integer (instead of being inferred as real)
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2024-05-24 22:43:34 +08:00 |
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AngeloJacobo
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88a913f8da
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clean verilator lint
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2024-05-24 21:51:20 +08:00 |
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AngeloJacobo
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237752fa3d
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clean printed details
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2024-05-06 17:11:04 +08:00 |
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AngeloJacobo
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1d1fd96893
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fixed bug when READ_SLOT and WRITE_SLOT is the same
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2024-05-05 21:15:02 +08:00 |
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AngeloJacobo
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22f6db696c
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automatically generate CL and CWL value based on ddr3 clock period
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2024-05-05 15:21:55 +08:00 |
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AngeloJacobo
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81a6ab32f9
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removed OPT parameters (no use), and add defines
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2024-05-05 13:32:37 +08:00 |
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Angelo Jacobo
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da8eaa5d91
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make internal test shorter during sim
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2024-04-21 13:06:19 +08:00 |
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Angelo Jacobo
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81865ea2f8
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make controller not dependent on chip-select cs_n
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2024-04-20 15:03:47 +08:00 |
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Angelo Jacobo
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25685e5769
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make internal test shorter during simulation
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2024-04-20 12:24:49 +08:00 |
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Angelo Jacobo
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31f02da699
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fixed rtoi error from vivado and add more options for speedbin and capacity
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2024-04-20 12:18:04 +08:00 |
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Angelo Jacobo
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eb5774d518
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add more comments
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2024-03-28 14:59:56 +08:00 |
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Angelo Jacobo
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b308e507d1
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add more comments
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2024-03-28 14:21:16 +08:00 |