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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 01:24:39 +02:00
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d916322b74a6aec0472b13eb173f1bcd279ba0f6
OpenRAM/compiler/characterizer
T
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Hunter Nichols df2f981a34 Adds checks to prevent characterization of redundant corners.
2020-02-19 15:59:26 -08:00
..
__init__.py
Removed unused characterization module.
2019-07-30 20:33:17 -07:00
bit_polarity.py
…
charutils.py
…
delay.py
Fixed issues with bitcell measurements variable names, made target write ports required during characterization
2020-02-19 15:34:31 -08:00
functional.py
Feedthru port edits.
2019-09-27 14:18:49 -07:00
lib.py
Adds checks to prevent characterization of redundant corners.
2020-02-19 15:59:26 -08:00
logical_effort.py
Made all cin function relate to farads and all input_load relate to relative units.
2019-08-08 01:57:04 -07:00
measurements.py
…
model_check.py
…
setup_hold.py
Remove extra print
2019-11-17 10:40:01 -08:00
simulation.py
Clean and simplify simulation code. Feedthru check added.
2019-09-06 12:09:12 -07:00
sram_op.py
…
stimuli.py
Remove unused test structures
2019-09-06 14:58:47 -07:00
trim_spice.py
…
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