OpenRAM/compiler/pgates
mrg d2c97d75a7 Add well contact and min area to power pin of precharge 2020-03-26 11:49:32 -07:00
..
pand2.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
pand3.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
pbuf.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
pdriver.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
pgate.py Add li_stack contact to ptx and pgate if it exists. 2020-03-23 16:55:38 -07:00
pinv.py Generalize pgate width based on nwell/pwell contacts 2020-02-25 17:09:07 +00:00
pinvbuf.py Clean up and generalize layer rules. 2019-12-17 11:03:36 -08:00
pnand2.py Remove unused contact in pnand2 2020-03-23 11:46:21 -07:00
pnand3.py Hack to fix pnand3 in freepdk45 2020-03-26 11:08:53 -07:00
pnor2.py Move up B input in pnor2 2020-03-23 13:49:08 -07:00
precharge.py Add well contact and min area to power pin of precharge 2020-03-26 11:49:32 -07:00
ptristate_inv.py Cleanup and rename vias. 2020-01-30 01:45:33 +00:00
ptx.py Skywater extraction mode for si unit scales 2020-03-24 12:41:15 -07:00
pwrite_driver.py Nwell fixes in pgates. 2020-02-06 16:20:09 +00:00
single_level_column_mux.py port_data: Each submodule now specifies their bl/br names 2020-02-12 15:00:50 +01:00