mrg
ffcf762784
Merge remote-tracking branch 'private/dev' into dev
2020-07-03 06:47:37 -07:00
Hunter Nichols
206b02a7ee
Merge branch 'dev' into characterizer_bug_fixes
2020-07-02 18:00:41 -07:00
Hunter Nichols
fb34338fdf
Removed debug statements
2020-07-02 18:00:02 -07:00
mrg
2a86f9015b
Merge remote-tracking branch 'private/dev' into dev
2020-07-02 16:51:06 -07:00
Hunter Nichols
119bd94689
Fixed warnings with single port characterization. Cleaned up some signal names.
2020-07-02 15:43:23 -07:00
mrg
d48f483248
Fix swapped instance bug in perimeter pins.
2020-07-01 15:10:20 -07:00
mrg
bed2e36550
Simplify write mask supply via logic
2020-07-01 14:44:48 -07:00
mrg
8cd1cba818
Fix missing via in wmask driver
2020-07-01 14:44:18 -07:00
mrg
c340870ba0
Channel route dout wires as well in read write ports
2020-07-01 14:44:01 -07:00
mrg
bb18d05f75
Move control output via inside module instead of perimeter
2020-07-01 11:33:25 -07:00
mrg
3d0f29ff3a
Fix missing via LVS issues. LVS passing for some 20 tests.
2020-07-01 09:22:59 -07:00
mrg
b07f30cb9e
Missing output via in control logic
2020-06-30 16:23:07 -07:00
mrg
3379f46da1
Fail unit test, but mention if LVS passes and DRC fails.
2020-06-30 16:22:44 -07:00
mrg
0a87691176
Run Calibre LVS even if DRC fails.
2020-06-30 15:27:10 -07:00
mrg
c1fedda575
Modifications for min area metal.
...
Made add_via_stack_center iterative instead of recursive.
Removed add_via_stack (non-center) since it isn't used.
Add min area metal during iterative via insertion.
2020-06-30 15:07:34 -07:00
mrg
011ac2fc05
Don't route to clk to perimeter on m2
2020-06-30 13:57:45 -07:00
mrg
a48ea52253
Add missing contact to vdd pins.
2020-06-30 13:26:38 -07:00
mrg
5626fd182e
Extra track in data bus. Remove old code.
2020-06-30 10:58:24 -07:00
mrg
eb11ac22f3
Widen pitch of control bus in bank.
2020-06-30 10:58:09 -07:00
mrg
8cedeeb3d9
Widen pitch of control bus in bank.
2020-06-30 10:57:41 -07:00
Matt Guthaus
9b939c9a1a
DRC/LVS and errors fixes.
...
Only enact pdb if assert fails in debug.error.
Only run drc/lvs one time in parse_info by saving result.
Cleanup drc/lvs output.
2020-06-30 07:16:05 -07:00
Hunter Nichols
0464e2df5d
Allowed bitline checks for multiple ports.
2020-06-30 01:37:52 -07:00
Hunter Nichols
c289637dab
Allowed sen's from multiple ports to be characterized
2020-06-29 23:18:31 -07:00
mrg
372a8a728e
Off by one error in channel spacing
2020-06-29 16:47:34 -07:00
mrg
459e3789b8
Change control layers in sky130.
2020-06-29 16:23:25 -07:00
mrg
bec948dcc3
Fix error in when to add vias for array power
2020-06-29 15:28:55 -07:00
mrg
4e7e0c5954
Skip test in sky130
2020-06-29 15:28:16 -07:00
Matt Guthaus
e97644c424
Only do reverse lookup on valid interconnect layers since layer numbers can be shared.
2020-06-29 14:42:24 -07:00
mrg
07d0f3af8e
Only copy end-cap pins to the bank level
2020-06-29 11:46:59 -07:00
mrg
1bc0775810
Only add pins to periphery
2020-06-29 10:03:24 -07:00
mrg
5f3a45b91b
Compute bus size separately for ports
2020-06-29 05:54:30 -07:00
mrg
47f541df0e
Fix bugs in channel route.
2020-06-28 16:58:28 -07:00
mrg
5285468380
All bitcells need a vdd/gnd pin
2020-06-28 15:09:47 -07:00
mrg
751eab202b
Move row addr flops away from predecode. Route spare wen separately on lower layer.
2020-06-28 15:06:29 -07:00
mrg
20324ab3c4
Revert write driver pin spacing
2020-06-28 14:55:58 -07:00
mrg
051c8d8697
Only add bitcells to dummy and replica rows and columns (the perimeter)
2020-06-28 14:47:54 -07:00
mrg
709535f90f
Fix right perimeter pin coordinate bug
2020-06-28 14:47:17 -07:00
mrg
225fc69420
Use preferred routing direction
2020-06-28 14:29:12 -07:00
mrg
4df02dad67
Move spare wen_dff to the right by spare columns
2020-06-28 14:28:43 -07:00
mrg
bc3de9db05
Pick correct side of pin in channel route.
2020-06-28 14:28:18 -07:00
mrg
e774314add
Separate write driver pins by M3 pitch
2020-06-28 14:14:48 -07:00
mrg
0c9f52e22f
Realign col decoder and control by 1/4 so metal can pass over
2020-06-28 07:15:06 -07:00
mrg
66ea559209
Use channel for dffs all at once
2020-06-27 08:23:12 -07:00
mrg
c10a6a29c0
Simplify precharge pin layer
2020-06-27 08:22:16 -07:00
mrg
609aa98c8b
Move write mask pin to left of cell to avoid sense amp
2020-06-27 08:21:53 -07:00
mrg
2bd498c39c
Change precharge layer to m3
2020-06-27 08:21:30 -07:00
mrg
a7ee17eb2d
Move output of sense amp to side like other techs
2020-06-26 15:29:27 -07:00
mrg
c07e20cbe4
Move mux select from li to m2 in sky130
2020-06-26 14:27:16 -07:00
mrg
94d7000717
Reduce output clutter from gds write
2020-06-26 12:16:54 -07:00
mrg
f57eeb88eb
PEP8 cleanup, multiple vdd/gnd support
2020-06-26 11:47:55 -07:00
mrg
Hunter Nichols