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5001 Commits

Author SHA1 Message Date
Matt Guthaus ffb5074192
Merge pull request #301 from bhagwat-rahul/update-tech-porting-docs 
Make porting.md more accurate with recent updates
 2026-07-18 15:33:33 -04:00
Matt Guthaus 847d3b4db2
Merge pull request #300 from bhagwat-rahul/fix-contact-email 
Remove dead contact us emails
 2026-07-18 15:30:09 -04:00
Rahul Bhagwat 64cd3b708f
make porting md more accurate post some updates 2026-07-19 00:55:29 +05:30
Rahul Bhagwat 4c93ec5608
remove dead email links 2026-07-19 00:35:57 +05:30
Matt Guthaus c4e94f25d3
Merge pull request #297 from Aurora7913/close-filehandles 
Fix python warnings about filehandles left open
 2026-06-27 14:52:18 -04:00
Maarten Boersma 448f0ce488
close version file after reading 2026-06-24 10:20:11 +02:00
Maarten Boersma d0fb2149d9
Because the logfile handle is opened everytime before writing a message, we should also close it after writing a line 2026-06-24 10:20:08 +02:00
Jesse Cirimelli-Low d309a25c4c update wmask test to work for sky130 single port 2026-05-14 19:46:42 -07:00
Jesse Cirimelli-Low 8c4f4ef27f when routing between the wordline drivers and the wordline pins of the crba, midden metal in the jog to resolve drc violations if needed 2026-05-14 19:25:27 -07:00
Jesse Cirimelli-Low 541b744e82 create separate nand cells for user drc sky130 cell 2026-05-14 16:21:29 -07:00
Jesse Cirimelli-Low cc9f294992 use more conservative metric for metal mergeing in array to power rail routing 2026-05-14 11:18:31 -07:00
Jesse Cirimelli-Low 269386e6b8 clean up code 2026-05-14 02:10:44 -07:00
Jesse Cirimelli-Low c3da65c33c sky130 dp bank passing 2026-05-14 01:58:41 -07:00
Jesse Cirimelli-Low 5222224936 route supplies from endcaps to power ring 2026-05-13 16:45:52 -07:00
Jesse Cirimelli-Low afca50c20b power ring routing optimized, stretch crba pins to edge of power ring to avoid drc errors 2026-05-13 12:35:08 -07:00
Jesse Cirimelli-Low 34b317ce7d remove debug print statements 2026-05-11 16:05:20 -07:00
Jesse Cirimelli-Low 9fcf61f031 merge in array generation branch 2026-05-11 13:09:52 -07:00
Jesse Cirimelli-Low e16d9eb0b4 make sky130-install now correctly merges with privded cells 2026-05-11 10:44:24 -07:00
Jesse Cirimelli-Low 2f8f9bc2e3 use python venv so we can still run make library 2026-05-11 10:44:24 -07:00
Jesse Cirimelli-Low 91d0eb1d2c use python venv with nix 2026-05-11 10:44:24 -07:00
Jesse Cirimelli-Low 45e58838d6 fix ciel repo 2026-05-11 10:44:24 -07:00
Jesse Cirimelli-Low c1e93ce686 add ciel to nix flake for pdk managementment 2026-05-11 10:44:24 -07:00
Jesse Cirimelli-Low cbd2bd7c2e switch from conda to nix for tooling 2026-05-11 10:44:24 -07:00
Jesse Cirimelli-Low c864427734 make contacts perpendicular to power rails to avoid drc violations 2026-05-07 15:03:53 -07:00
Jesse Cirimelli-Low c3987f2537 change power ring spacing from magic numbers to drc based 2026-05-07 14:18:58 -07:00
Jesse Cirimelli-Low e7829cf641 allow tech file to specify connection to power rail per net 2026-05-06 10:42:02 -07:00
Jesse Cirimelli-Low 541d4ff572 parameterize how power ring is connected to crba 2026-05-06 09:50:56 -07:00
Jesse Cirimelli-Low 28fef79202 make sky130-install now correctly merges with privded cells 2026-05-04 17:32:07 -07:00
Jesse Cirimelli-Low 797664c343 update sky130 cell paths 2026-05-04 17:15:49 -07:00
Jesse Cirimelli-Low c089ff0e78 update git ignore so we can track just our sky130 cells 2026-05-04 17:07:33 -07:00
Jesse Cirimelli-Low 88cf3ae401 use python venv so we can still run make library 2026-05-04 16:56:27 -07:00
Jesse Cirimelli-Low 5bd5293b4e use python venv with nix 2026-05-04 16:39:33 -07:00
Jesse Cirimelli-Low 07b33b3dfd fix ciel repo 2026-05-04 16:25:26 -07:00
Jesse Cirimelli-Low 4e93ba0424 add ciel to nix flake for pdk managementment 2026-05-04 13:01:52 -07:00
Jesse Cirimelli-Low 03c5a58758 add sp non cypress bitcells 2026-05-04 12:47:00 -07:00
Jesse Cirimelli-Low e4a895ecb0 fix verbosity level 2026-04-30 13:02:03 -07:00
Jesse Cirimelli-Low a5c879f510 Merge remote-tracking branch 'openram_local/array_gen' into merge/full-array-gen-into-dev 
# Conflicts:
#	technology/sky130/custom/sky130_col_cap_array.py
 2026-04-30 12:43:19 -07:00
Jesse Cirimelli-Low ddac4254ec switch from conda to nix for tooling 2026-04-30 12:00:56 -07:00
Jesse Cirimelli-Low 2780fda35c all sky130 crba passing 2026-04-28 23:22:40 -07:00
Jesse Cirimelli-Low 88241ca685 add fix for cypress sp wls 2026-04-28 17:19:54 -07:00
Jesse Cirimelli-Low 5077282180 count wordlines from bottom going up 2026-04-28 14:04:42 -07:00
Jesse Cirimelli-Low c7f3ac33cd sky130 cypress dp working with offset relative to crba 2026-04-27 17:24:13 -07:00
Jesse Cirimelli-Low 3e569feebf Merge branch 'dev' into array_gen 2026-04-22 01:38:59 -07:00
Jesse Cirimelli-Low cb7f117daa squash commits 2026-04-22 01:33:47 -07:00
Matt Guthaus f2db9fe2de
Merge pull request #291 from goobber-gawber/modernize2 
compiler: gdsMill: Modernize codebase.
 2026-04-17 07:25:26 -07:00
Gabriel Wicki 5cd43442b8 compiler: gdsMill: Modernize codebase. 
* compiler/gdsMill/pyx/graph/axis/tick.py: Modernize.
 2026-04-17 13:14:03 +02:00
Jesse Cirimelli-Low 5fd548582f bump cell lib version for dual port fixes 2026-04-14 15:10:30 -07:00
Jesse Cirimelli-Low 515591a422 dual port rba lvs clean again with cell library changes 2026-04-14 14:48:26 -07:00
Matthew Guthaus 9274fbd4f2 Merge branch 'stable' into dev 2026-04-08 11:26:03 -07:00
Matthew Guthaus 449781d239 Revert "Revert "Update defunct code"" 
This reverts commit d142b906ee.
 2026-04-08 11:25:48 -07:00