mirror of https://github.com/VLSIDA/OpenRAM.git
Merge pull request #301 from bhagwat-rahul/update-tech-porting-docs
Make porting.md more accurate with recent updates
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# Porting to a New Technology
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If you want to support a new technology, you will need to create:
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+ a setup script for each technology you want to use
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+ a setup script (`<technology>/__init__.py`) for each technology you want to use
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+ a technology directory for each technology with the base cells
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We provide two technology examples for [SCMOS] and [FreePDK45]. Each
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@ -15,7 +15,7 @@ specific technology (e.g., [FreePDK45]) should be a subdirectory
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* `replica\_cell\_1rw.gds`
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* `dummy\_cell\_1rw.gds`
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* `sp_lib` folder with all the `.sp` (premade) library netlists for the above cells.
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* `layers.map`
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* `layers.map` (for workflows using Calibre verification otherwise inlined into tech.py)
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* A valid tech Python module (tech directory with `__init__.py` and `tech.py`) with:
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* References in tech.py to spice models
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* DRC/LVS rules needed for dynamic cells and routing
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