Michael Timothy Grimes
4ea2a70a1b
removing unnecessary unit test for pbitcell
2018-02-19 10:58:08 -08:00
mguthaus
5e8dff1e90
Fix unit tests with newest RBL delays. Fix tech problem with new spice models.
2018-02-16 13:54:05 -08:00
mguthaus
c1c1ba38a3
Fix unit test to have fanout.
2018-02-16 11:53:38 -08:00
Matt Guthaus
9559421ca8
Connect dff array clk in rows and columns.
2018-02-14 16:46:26 -08:00
Matt Guthaus
2d87dcda46
dff array done except for clock net
2018-02-14 16:03:29 -08:00
Matt Guthaus
0804a1eceb
Add new DFF. Create DFF module. Start dff_array, not tested.
2018-02-14 15:16:28 -08:00
mguthaus
767990ca3b
Update golden lib tests. Add new generic SCMOS models. Fix tech error with new msflop_in_cap name.
2018-02-13 15:54:50 -08:00
Matt Guthaus
a12ebeed9f
Add multiple process corners. Unit tests use nominal corner only. Add fake SCMOS nominal models, but they are broken.
2018-02-12 09:33:23 -08:00
mguthaus
1795dc5677
Fix three unit tests to work with new lib corner files.
2018-02-11 20:43:41 -08:00
mguthaus
f690532563
Add new corner-based lib files to unit tests.
2018-02-11 16:35:10 -08:00
Matt Guthaus
b75eef3684
Fix syntax error.
2018-02-10 08:02:59 -08:00
Matt Guthaus
f86985821a
Begin modifications for corner-based characterization. Made stimuli.py a class. Golden output files are not updated.
2018-02-09 15:33:03 -08:00
Matt Guthaus
3c86f94549
Change argument name for lib in tests as well.
2018-02-08 15:28:49 -08:00
Michael Timothy Grimes
ce83b67350
Merge branch 'master' of https://github.com/mguthaus/OpenRAM into multiport
2018-02-08 14:27:53 -08:00
Michael Timothy Grimes
b90f5c9a59
pbitcell is now a multiport cell with a read transistor that connects to RBL and RROW and a read access transistor that connects to Q and gnd
...
current commit works without drc errors on freepdk45 but has drc rules not included in scn3me_subm. Does have lvs errors
adding several unit tests: the basic one that tests the full functionality of the pbitcell, one with no write ports, and one with no read ports
2018-02-08 14:21:15 -08:00
mguthaus
e8f658d356
Add updated non-pruned unit test results.
2018-02-07 19:35:21 -08:00
mguthaus
63ce754c72
Update unit test results
2018-02-07 18:48:22 -08:00
Matt Guthaus
2413304f4e
Update replica bitline test for new parameters. Add small test and a larger test.
2018-02-07 15:15:19 -08:00
Matt Guthaus
1a491f3cd0
Make temp directory unique for test 30. Update LEF files after delay chain size change.
2018-02-07 15:05:21 -08:00
mguthaus
3af1bbba26
Updated delay tests with new delays including ps, pd, as, ad.
2018-02-06 07:58:25 -08:00
mguthaus
c3592b3d46
Added new timing tests with ps,pd,as,ad caps included.
2018-02-06 05:26:27 -08:00
mguthaus
e01d5b7c61
Disable virtual connects at top level LVS with Calibre.
2018-02-05 14:52:51 -08:00
Matt Guthaus
92095e52f7
Update new LEF files for unit tests.
2018-02-05 10:27:56 -08:00
Matt Guthaus
f21ff38cae
Simplify via offsets in replica bitline. Route clk_bar in control over supply rail until we get channel router working.
2018-02-05 10:22:38 -08:00
Matt Guthaus
7127895270
Update LEF files for unit tests
2018-02-02 15:51:29 -08:00
Matt Guthaus
9d7dc4c552
Reset even if not purging temp files.
2018-02-02 14:26:09 -08:00
Matt Guthaus
fb90b8f5fe
Fix pin nameon sense amp spice. Fix NAND2 bug in hierarchical decoder.
2018-02-02 14:08:56 -08:00
Matt Guthaus
d552d88f45
Add -d option to not delete temp directory on successful runs.
2018-02-01 11:53:02 -08:00
Matt Guthaus
8ef1e0af2c
Replace LEF files with new changes.
2018-02-01 05:43:37 -08:00
Matt Guthaus
9fea4a1a2d
Do not require hspice during tests. Check if a valid simulator is found, however.
2018-01-31 16:21:43 -08:00
Matt Guthaus
590f6e01d1
Fix assertion error syntax problem. Do not require hspice for functional test. Improve delay fail error message.
2018-01-31 15:38:02 -08:00
mguthaus
4273a3717d
Clean up messages.
2018-01-31 11:54:20 -08:00
mguthaus
4aee700331
Modify unit tests to distinguish between FAIL and ERROR. Move comparison utilities into our derived unit test class.
2018-01-31 11:48:41 -08:00
Matt Guthaus
1175f515c8
Add descriptive exceptions along with cleanup in unit test checking.
2018-01-31 10:35:51 -08:00
Matt Guthaus
264d55b16c
Remove temp files
2018-01-30 08:05:50 -08:00
Matt Guthaus
8fcb551953
Only perform DRC not LVS on transistors
2018-01-30 08:03:54 -08:00
Matt Guthaus
1d9274621a
Only remove files when cleaning temp dir
2018-01-30 07:58:31 -08:00
Matt Guthaus
56770f558f
Consolidate checking into our own unit test class. Remove all files in temp dir after each test, not just spice and gds.
2018-01-29 16:59:29 -08:00
Michael Timothy Grimes
fb2572bd71
Merge branch 'master' of https://github.com/mguthaus/OpenRAM into multiport
2018-01-28 21:44:22 -08:00
Matt Guthaus
e46a4fb115
Use any spice for the functional tests.
2018-01-26 13:53:11 -08:00
Matt Guthaus
028146f3c2
Add output explaining error for not finding simulator in unit tests.
2018-01-26 13:23:11 -08:00
Matt Guthaus
369aa85cd2
Fail simulation tests if correct spice is not found. Correctly load spice characterizer.
2018-01-26 13:00:25 -08:00
Matt Guthaus
50107636a0
Fail test early if spice simulator is not found.
2018-01-26 12:47:32 -08:00
Matt Guthaus
2468f224d9
SCMOS library cells passing LVS (with property errors though). Permute must be enabled before compare, duh.
2018-01-22 17:14:39 -08:00
Matt Guthaus
fb2ed1d46c
Add wells to fix DRC errors in SCMOS library cells.
2018-01-22 16:28:20 -08:00
Matt Guthaus
10ced33127
Fixed command line arguments to take priority over config file. Any option can be specified in config file now.
2018-01-21 11:21:09 -08:00
Matt Guthaus
84ec7a5be0
Convert unit tests to use new options as well.
2018-01-19 17:23:38 -08:00
Matt Guthaus
490a70dee9
Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file.
2018-01-19 16:38:19 -08:00
Matt Guthaus
efa465757c
Remove dead code ptx_port.
2018-01-19 16:19:05 -08:00
Matt Guthaus
243097cb33
Remove print statement in magic.py
2018-01-12 14:45:11 -08:00
Michael Timothy Grimes
mguthaus