754 Commits

Author	SHA1	Message	Date
mrg	12fd60e8c3	Fix pbitcell array test	2020-09-09 12:02:09 -07:00
mrg	7bb21fb73f	Updates to local and global arrays to make bitline and wordlines consistent.	2020-09-09 11:54:46 -07:00
mrg	c1c631abe1	Global bitcell array passes LVS/DRC	2020-09-01 10:57:49 -07:00
mrg	7bdce3ca9a	Don't make dummy bitlines pins for simplicity	2020-09-01 09:55:23 -07:00
mrg	11a82b7283	Fixed local bitcell array for single and dual port	2020-08-27 14:03:05 -07:00
mrg	e92337ddaf	Separate get_ and get_all for bitlines and wordlines	2020-08-25 17:08:48 -07:00
mrg	28bd93bf51	Still working on array refactor	2020-08-25 11:50:44 -07:00
mrg	8dee5520e0	Standardize array names independent of bitcell	2020-08-21 13:44:35 -07:00
mrg	b762580ee2	Skip global test for now	2020-08-19 11:36:21 -07:00
mrg	224e359208	Fix pin order for replica array	2020-08-18 15:59:05 -07:00
mrg	f58fc6579f	Rename local/global tests	2020-08-18 15:58:44 -07:00
mrg	e3e4bac922	Fix replica bitcell array for right only RBL	2020-08-18 15:47:52 -07:00
mrg	59d65c46c3	Fix bug in not adding RBLs in local bitcell array	2020-08-18 15:11:10 -07:00
mrg	b288bba43e	Add global bitcell array test	2020-08-18 14:29:23 -07:00
mrg	99e252d6d4	Update interface of RBL array	2020-08-17 17:19:07 -07:00
mrg	b1e55f9072	Add local bitcell array	2020-08-17 15:14:42 -07:00
mrg	797c41c750	Skip local bitcell array test	2020-08-13 14:36:39 -07:00
mrg	8e890c2014	Replica bitcell with all the fixings	2020-08-11 15:00:29 -07:00
mrg	eef97ff215	Reabstracting bit and word line names.	2020-08-06 11:17:49 -07:00
mrg	2fa561f98f	Local bitcell array edits. Skip test by default.	2020-07-29 10:08:13 -07:00
mrg	c260297366	Allow replica_bitcell_array without the replica columns for local wordlines.	2020-07-27 16:22:21 -07:00
mrg	69cab42676	Add pbuf_dec gate	2020-07-27 13:59:55 -07:00
mrg	26b01e37c6	Fix pbuf test info	2020-07-27 13:59:35 -07:00
mrg	2991534d3f	Drafting local bitline stuff.	2020-07-23 17:15:39 -07:00
mrg	e1967dc548	Draft local and global arrays. Ensure rows before cols in usage.	2020-07-23 14:43:14 -07:00
mrg	3379f46da1	Fail unit test, but mention if LVS passes and DRC fails.	2020-06-30 16:22:44 -07:00
mrg	0a87691176	Run Calibre LVS even if DRC fails.	2020-06-30 15:27:10 -07:00
mrg	4e7e0c5954	Skip test in sky130	2020-06-29 15:28:16 -07:00
mrg	af4ed3dd6e	Skip riscv func test for time sake	2020-06-26 06:50:45 -07:00
mrg	76e5389c33	Change riscv func test name	2020-06-25 17:43:17 -07:00
mrg	9eb1b500ea	Skip phys riscv test	2020-06-25 17:31:23 -07:00
mrg	7220b23402	Add riscv unit tests	2020-06-25 15:34:18 -07:00
mrg	b3d1161957	Add u+x permissions to new tests	2020-06-24 08:19:25 -07:00
Joey Kunzler	22ed725a35	made 1rw_1r tests for write driver and wmask, fixed typo in portdata_wmask_1rw_1r_test	2020-06-23 18:16:14 -07:00
mrg	22c821f5d8	Change port_address test to 256 for riscv	2020-06-23 15:40:00 -07:00
mrg	1a528f9739	Skip and4_dec test	2020-06-23 10:08:28 -07:00
mrg	92fc30005c	Use factory in and_dec tests	2020-06-22 16:55:49 -07:00
mrg	5872f553e1	Rename tests for consistency	2020-06-19 08:53:35 -07:00
mrg	239b3ea007	Make wmask test a 1rw/1r	2020-06-19 08:49:48 -07:00
mrg	a862cf3cb2	Test more single level col mux configs	2020-06-15 10:17:54 -07:00
mrg	6c04166876	Update port data wmask tests	2020-06-15 06:05:05 -07:00
mrg	9930b5f3f6	Do not run tapless unit tests	2020-06-14 14:18:25 -07:00
mrg	33a32101c9	DRC and LVS fixes for pinv_dec	2020-06-12 15:23:51 -07:00
mrg	dff28a9997	Merge branch 'tech_migration' into dev	2020-06-10 17:09:05 -07:00
mrg	fdf92d0da1	Rename test 14	2020-06-10 16:41:26 -07:00
mrg	469cd260b9	Change bitcell array name to match	2020-06-10 14:54:20 -07:00
mrg	f2c45a230e	Add new replica column test. Add more skip tests.	2020-06-10 11:00:00 -07:00
mrg	10be2d08b5	Full path to skip tests file	2020-06-10 10:23:05 -07:00
mrg	c119e60e79	Add more s8 skip tests	2020-06-10 10:14:52 -07:00
mrg	d4fc88124a	Rename dff_buf test	2020-06-09 17:18:19 -07:00