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OpenRAM
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941 Commits

Author SHA1 Message Date
Matt Guthaus dc73e8cb60 Odd bug that instances were not properly rotated. 2018-10-24 16:12:27 -07:00
Matt Guthaus 7e2bef624e Continue routing rails in same layer after a blockage 2018-10-24 12:32:27 -07:00
Hunter Nichols a711a5823d Merged dev and fix conflicts in geometry.py 2018-10-24 10:52:22 -07:00
Matt Guthaus cccde193d0 Add ngspice equivalents of RUNLVL 2018-10-24 10:31:27 -07:00
Matt Guthaus 5f17525501 Added run-level option for write_control and enabled fast mode in functional tests 2018-10-24 09:32:44 -07:00
Matt Guthaus 33c716eda8 Rename psram bank test like sram bank testss 2018-10-24 09:08:54 -07:00
Matt Guthaus e90f9be6f5 Move replica bitcells to new bitcells subdir 2018-10-24 09:06:29 -07:00
Hunter Nichols 5c8a00ea1d Fixed pruned golden lib file from error in last commit. 2018-10-24 00:55:55 -07:00
Hunter Nichols da1b003d10 Fixed multiport lib files not generating the correct number of signals. Move setup time from DOUT to DIN in lib file. Altered golden files with these changes. 2018-10-24 00:17:08 -07:00
Hunter Nichols 016604f846 Fixed spacing in golden lib files. Added column mux into analytical model. 2018-10-24 00:16:26 -07:00
Hunter Nichols 53cb4e7f5e Fixed lib files to be syntactically correct with multiport. Fixed issue in geometry.py that prevented netlist_only option from working. 2018-10-22 23:33:01 -07:00
Hunter Nichols 62439bdac6 Fixed merge conflicts with sram.py 2018-10-22 17:29:14 -07:00
Hunter Nichols 4f08062268 Added custom 1rw+1r bitcell. Testing are currently failing. 2018-10-22 17:02:21 -07:00
Michael Timothy Grimes cda2e93cd7 Adding fix to netlist_only mode in geometry.py. Uncommenting functional tests and running both tests in netlist_only mode. 2018-10-22 09:17:03 -07:00
Michael Timothy Grimes 2053a1ca4d Improved debug comments for functional test 2018-10-22 01:09:38 -07:00
Michael Timothy Grimes 1a0568f244 Updating comments and cleaning up code for pbitcell. 2018-10-21 19:10:04 -07:00
Matt Guthaus ab7a83b7a5 Remove old setup.tcl and edit one in tech dir 2018-10-20 15:20:15 -07:00
Matt Guthaus e48e12e8cd Skip non-working 1bank tests for now. 2018-10-20 14:55:11 -07:00
Matt Guthaus 38a8c46034 Change non-preferred route costs. 2018-10-20 14:47:24 -07:00
Matt Guthaus 7591f25a2e Merge branch 'dev' into supply_routing 2018-10-20 14:29:19 -07:00
Matt Guthaus 5276943ba2 Remove temp log file 2018-10-20 14:26:30 -07:00
Matt Guthaus 4c25bb09df Fixed supply end-row via problem by restricting placement 2018-10-20 14:25:32 -07:00
Matt Guthaus f5e68c5c32 Move power pins in hierarchical decoder to be further. Strap rails instead for redundant vias. 2018-10-20 12:54:12 -07:00
Matt Guthaus f9738253c6 Remove warning of track space and floor the space function. 2018-10-20 11:53:52 -07:00
Matt Guthaus a1f2a5befe Convert supply tracks to sets for simpler algorithms. 2018-10-20 10:33:10 -07:00
Matt Guthaus 0aad61892b Supply router working except for off by one rail via error 2018-10-19 14:21:03 -07:00
Matt Guthaus 233a1425e4 Flatten bitcell array in netgen for now. See issue 52 2018-10-19 09:13:17 -07:00
jcirimel 74b806fa38
Merge pull request #54 from VLSIDA/datasheet_gen 
flask_table check fix
 2018-10-18 15:12:04 -07:00
Jesse Cirimelli-Low 1b4383b945 moved flask_table warning from sram.py to datasheet_gen.py 2018-10-18 09:58:19 -07:00
Jesse Cirimelli-Low b9990609bf provides warning on missing flask packages, does not generate html on missing packages 2018-10-18 07:21:03 -07:00
Michael Timothy Grimes a06a0975db Removed L shaped routing from gnd contact to wordlines in replica bitline. Corrected slight DRC errors. Optimizations to pbitcell. 2018-10-18 07:05:47 -07:00
Jesse Cirimelli-Low ab6afb7ca8 fixed html typos, added logo, added placeholder timing and current, began ports section 2018-10-17 19:27:09 -07:00
Matt Guthaus 4bf1e206e2 Merge branch 'dev' into supply_routing 2018-10-17 09:47:18 -07:00
Matt Guthaus 5d6944953b Fix char_result rename collision 2018-10-17 09:38:26 -07:00
Michael Timothy Grimes d6a9ea48ac Working out bugs in psram functional test for SCMOS. Commenting out for now. 2018-10-17 07:45:24 -07:00
Michael Timothy Grimes a27cdb4fbc Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-10-17 07:32:03 -07:00
Michael Timothy Grimes e60deddfea adding 6T transistor size parameters to tech files for use in pbitcell. 2018-10-17 07:28:56 -07:00
Michael Timothy Grimes 69a1560186 Changing the location of the vdd contact in precharge to avoid drc errors when the bitlines are close to the edge of the cell. Correcting replica bitcell function in pbitcell. 2018-10-16 06:57:53 -07:00
Matt Guthaus 5cb3a24b19 Fix supply rail step size to place alternating rails 2018-10-15 13:58:40 -07:00
Matt Guthaus e2cfd382b9 Fix print check regression 2018-10-15 13:23:31 -07:00
Matt Guthaus a165446fa7 First implementation of multiple track spacing wide DRCs in routing grid. 2018-10-15 11:25:51 -07:00
Matt Guthaus d60986e590 Don't skip grid format checks 2018-10-15 11:21:07 -07:00
Matt Guthaus d855d4f1a6 Moving wide metal spacing to routing grid level 2018-10-15 09:59:16 -07:00
Michael Timothy Grimes c8c70401ae Redesign of pbitcell for newer process technolgies. 2018-10-15 06:29:51 -07:00
Matt Guthaus 1c426aad29 Merge remote-tracking branch 'origin/datasheet_gen' into supply_routing 2018-10-12 20:55:57 -07:00
Matt Guthaus ce8c2d983d Update all drc usages to call function type 2018-10-12 14:37:51 -07:00
Jesse Cirimelli-Low afba54a22d added analytical model support, added proper output with sram.py 2018-10-12 13:22:12 -07:00
Matt Guthaus 5e9fe65907 Remove banks from example configs 2018-10-12 10:23:34 -07:00
Matt Guthaus 4932d83afc Add design rules classes for complex design rules 2018-10-12 09:44:36 -07:00
Michael Timothy Grimes d1701b8a2a Removing extra functional test and changing name to a more general form. Spice exe can just be selected from the command line with -s. 2018-10-12 06:29:59 -07:00