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OpenRAM
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4797 Commits

Author SHA1 Message Date
Hunter Nichols 7df36a916b Added an exclusion for unused column mux paths to prevent multiple outputs paths in graph. 2021-06-14 13:51:52 -07:00
Hunter Nichols 4d22201055 Changed name of regression test since we currently only test the delay. 2021-06-14 10:57:20 -07:00
mrg 159d0ed603 Fix s_en spacing problem. 2021-06-13 15:08:05 -07:00
mrg 53107a8322 Add ring test 2021-06-13 15:03:41 -07:00
mrg d6a72aed37 Add 2x1 perimter pins to satisfy minimum area rule. 2021-06-13 15:00:46 -07:00
mrg 2e23fffadd Fix comment 2021-06-13 14:18:55 -07:00
Jesse Cirimelli-Low 73cc6b3891 uncomment 4x16 decoder 2021-06-11 18:20:36 -07:00
Jesse Cirimelli-Low bee9b07516 fix decoder routing 2021-06-11 18:19:07 -07:00
Jesse Cirimelli-Low 2e72da0e53 rotate input to rail contacts for drc 2021-06-10 14:01:28 -07:00
Jesse Cirimelli-Low 247a388ab5 Merge branch 'dev' into laptop_checkpoint 2021-06-09 18:25:45 -07:00
Jesse Cirimelli-Low 10f561648f remove hierarchical decoder vertial m1 above pins 2021-06-09 18:24:21 -07:00
mrg 8964abc2b7 Change simulator based on one in use. 2021-06-09 16:02:32 -07:00
Hunter Nichols 4ec2e1240f Merge branch 'dev' into automated_analytical_model 2021-06-09 15:45:41 -07:00
Hunter Nichols c50ffe70b3 Added more configs for model and respective data. 2021-06-09 15:42:15 -07:00
Hunter Nichols ccf98ad5a6 Added accuracy check in regression model test. 2021-06-09 13:44:42 -07:00
Hunter Nichols 7a60eabdfe Add more freepdk45 data from regression model. 2021-06-09 13:31:38 -07:00
Hunter Nichols b6b20c1f43 Removed level 0 debug statements for bitlines naming. 2021-06-09 12:53:31 -07:00
Hunter Nichols f25dcf1b63 Fixed issue with bitline name warning occuring when no issue is present. 2021-06-09 12:52:26 -07:00
mrg c143be12d3 Merge branch 'dev' into xyce 2021-06-09 11:43:44 -07:00
mrg 23fe8ccffa Merge branch 'xyce' of github.com:VLSIDA/PrivateRAM into xyce 2021-06-09 11:38:44 -07:00
Hunter Nichols a73bfe6c2c Added more configs for model and data from scn4m_subm run. 2021-06-09 10:35:58 -07:00
mrg a1cb20878d Swap LH/HL hold times in sky130. 2021-06-08 11:14:27 -07:00
Hunter Nichols 3d82718f5a Changed neural network model to be sklearn based 2021-06-07 12:26:45 -07:00
mrg 27c6a13923 Back out drc listall count for detecting errors 2021-06-04 15:51:50 -07:00
mrg cf61096936 Merge branch 'laptop_checkpoint' into dev 2021-06-04 15:22:37 -07:00
Hunter Nichols 331e6f8dd5 Added functions for testing accuracy of current regression model and associated test. 2021-06-04 15:04:52 -07:00
Hunter Nichols 84783bbac5 Added more configs for model generation 2021-06-04 13:38:17 -07:00
Hunter Nichols 54639bbb94 Added more data for regression models 2021-06-04 13:37:21 -07:00
mrg 6643759345 Add back drc listall with correct output. 2021-06-04 11:06:39 -07:00
mrg 53791d79c8 spacing must be two extensions (one for each cell) 2021-06-04 08:56:06 -07:00
mrg cc4c6e909b Check if s_en exists before using it 2021-06-04 07:48:26 -07:00
mrg 4107c983e2 Make sure channel route is below s_en 2021-06-04 07:14:49 -07:00
mrg 537fd6eff9 Use None instead of empty string for tool names. 2021-06-01 16:41:14 -07:00
mrg 1ded978256 Change nwell from gnd to vdd. dnwell space added. 2021-06-01 15:10:55 -07:00
Hunter Nichols 0692593236 Specified line terminator in sim_data output to prevent carriage returns 2021-06-01 14:49:08 -07:00
Hunter Nichols 35ce838c8a Fixed issues with makefile with removal of prerequisite 2021-05-31 01:07:12 -07:00
Hunter Nichols 4da9d3beaf Removed config file as a prereq in makefile due to errors. Changes in config file will not result in a re-simming of that configuration now and will require a clean. 2021-05-30 23:58:24 -07:00
Hunter Nichols ccfda16ab2 Changed makefile to include okay files to indicate which configs have already been simulated for the existing models. 2021-05-30 22:19:56 -07:00
Jesse Cirimelli-Low 24b45ca2d4 use flat magic files instead of gds flatten subcell 2021-05-29 16:54:36 -07:00
Jesse Cirimelli-Low 131ca42512 merge in dev 2021-05-29 16:11:21 -07:00
Jesse Cirimelli-Low 97f43e31f0 remove breakpoint 2021-05-29 16:08:31 -07:00
mrg e944a5ec02 Use open_pdks setup.tcl if available. Set vdd/gnd/sub in run_ext.sh 2021-05-28 16:39:48 -07:00
Jesse Cirimelli-Low 6705f99855 merge in dev 2021-05-28 14:06:23 -07:00
Jesse Cirimelli-Low 1a894a99dd push bias pins to top level power routing 2021-05-28 13:41:58 -07:00
mrg 9e8d39f911 Remove debug gds dump 2021-05-28 13:31:19 -07:00
mrg d6d0df97f8 Get rid of write_size error when write_size==word_size 2021-05-28 13:06:12 -07:00
mrg 77f221d859 Separate supply pin type from route supplies option 2021-05-28 11:55:50 -07:00
mrg 013c5932a0 Valid type is tree not single 2021-05-28 11:26:41 -07:00
mrg f6587badad Improve supply routing for ring and side pins 2021-05-28 10:58:30 -07:00
Hunter Nichols da67edbde8 Changed input format for delay module in xyce delay test. 2021-05-26 20:11:30 -07:00