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OpenRAM
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3,471 Commits 4 Branches 63 Tags 78 MiB
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118 Commits

Author SHA1 Message Date
mrg 7c001732b1 Add destination file as dot file 2021-05-18 14:54:13 -07:00
mrg 191b382171 Change magic to use OPENRAM_MAGICRC if defined. 2021-05-18 13:27:11 -07:00
Matt Guthaus 30fc81a1f0 Update copyright year. 2021-01-22 11:23:28 -08:00
mrg 408ea15228 Ordering bug fixed in Magic. 2021-01-12 16:20:26 -08:00
mrg 9a6ca328f6 Temporarily disable flatten and readonly in magic DRC 2021-01-06 09:42:56 -08:00
mrg 348001b1c8 Supply tree uses signal grid. PEP8 cleanup. 2020-12-21 13:51:50 -08:00
mrg bad735fd89 Uncomment flatten as it is neeeded for correct extraction 2020-12-17 15:24:44 -08:00
mrg 9d9f0fddf0 Only do total DRC count. 2020-12-15 13:00:20 -08:00
mrg 35a6b1d2ee Fix copy gds/sp error with new relative paths 2020-12-11 10:22:35 -08:00
mrg 38bf12771b Make DRC/LVS scripts use relative paths 2020-12-11 10:06:00 -08:00
mrg 9717794400 Remove extra debug statement 2020-12-08 11:59:14 -08:00
mrg ac60c4fe3c Initial maglef flow for sky130 2020-12-08 11:56:23 -08:00
mrg bad1274bdb Use internal name for col/row caps. gds ordered read enabled. 2020-12-03 10:03:47 -08:00
mrg 3c115f0ecb LVS using Netgen not Magic 2020-12-02 11:26:00 -08:00
mrg c3472b5bc5 Remove old commented code 2020-12-01 13:27:50 -08:00
mrg b621c3bdc0 Allow verbose output from scripts with one -v and not unit test 2020-12-01 11:18:27 -08:00
Tim 'mithro' Ansell fa5296e621 Improving magic verification shell scripts. 
* Output header at start of script.
 * Output footer at end.
 * Add a bunch more progress report to magic output.
 * Make script return the same exit code as magic.
 2020-11-29 12:19:19 -08:00
mrg e6a7ecae84 Fix missing default path in pex 2020-11-12 14:43:57 -08:00
mrg 537e862d48 Add -full to LVS script 2020-11-10 20:38:41 -08:00
mrg 03dad01e4c Use readspice to define ports from sp netlist in Magic extract. 2020-11-10 17:06:24 -08:00
mrg 56c2222c2b Temp comment Magic GDS filter code. 2020-11-10 13:37:18 -08:00
mrg 10542d6cc3 Output DRC and LVS run files to output directory. 2020-11-09 11:12:31 -08:00
mrg a52aac5f31 Add gds flatten option for Magic 2020-11-05 13:12:08 -08:00
mrg 9a38f7a5f4 Enable gds readonly in Magic DRC/LVS 2020-11-04 10:50:53 -08:00
mrg da721a677d Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
mrg 1e24b780bb Initial pex sram test. 2020-10-02 13:32:52 -07:00
mrg b32c123dab PEP8 cleanup. Un-hard-code bitcell layers. Remove dead variable. 2020-10-01 11:10:18 -07:00
mrg 11f2b6b809 Do not do final verification if supplies were not routed 2020-09-15 13:39:00 -07:00
mrg 652f160aca Merge branch 'wlbuffer' into dev 2020-08-25 15:50:08 -07:00
mrg 856cce1e62 Add -json for detailed LVS output 2020-08-25 13:58:28 -07:00
jcirimel 9cecf367ee Merge branch 'dev' into pex 2020-08-17 17:49:41 -07:00
mrg 2c43d315db Revert gds readonly true 2020-08-17 12:19:23 -07:00
mrg 604e433e22 Add readonly true for Magic scripts 2020-08-14 10:40:31 -07:00
jcirimel 38648027d0 fix pinv unit test 2020-08-04 04:40:20 -07:00
jcirimel 02e65a00ef update pex to work with dev changes 2020-08-03 17:14:34 -07:00
jcirimel 1d9296ceb1 fix magic.py conflict 2020-07-21 11:50:25 -07:00
jcirimel df4a231c04 fix merge conflicts 2020-07-21 11:38:34 -07:00
mrg a989ea63a0 Move magic/netgen files to tech dir 2020-07-09 11:33:14 -07:00
Matt Guthaus 9b939c9a1a DRC/LVS and errors fixes. 
Only enact pdb if assert fails in debug.error.
Only run drc/lvs one time in parse_info by saving result.
Cleanup drc/lvs output.
 2020-06-30 07:16:05 -07:00
mrg a2d160dbf5 Copy magic config for filter code 2020-06-19 13:40:45 -07:00
mrg 7dfc462ef6 Add magic filter before calibre for sky130 2020-06-15 13:58:26 -07:00
mrg 443b8fbe23 Change s8 to sky130 2020-06-12 14:23:26 -07:00
jcirimel 575278998d write only used bitcells to top level in stim and pex output 2020-05-28 23:56:15 -07:00
jcirimel 0f9e38881c update stim for large pex layouts 2020-05-04 03:05:33 -07:00
mrg 2f353187ba Skywater extraction mode for si unit scales 2020-03-24 12:41:15 -07:00
Jesse Cirimelli-Low 6e070925b6 update magic for multiport 2020-01-28 02:32:34 +00:00
Jesse Cirimelli-Low 1a97dfc63e syncronize bitline naming convention betwen bitcell and pbitcell 2020-01-27 11:50:43 +00:00
Jesse Cirimelli-Low d42cd9a281 pbitcell working with bitline adjustments 2020-01-27 10:03:31 +00:00
jcirimel 40c01dab85 fix bl in stim file 2020-01-21 01:44:15 -08:00
jcirimel 73691f6054 fix bug in top level bitline label placement 2020-01-21 00:20:52 -08:00