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OpenRAM
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4034 Commits

Author SHA1 Message Date
Jesse Cirimelli-Low cc9f294992 use more conservative metric for metal mergeing in array to power rail routing 2026-05-14 11:18:31 -07:00
Jesse Cirimelli-Low 269386e6b8 clean up code 2026-05-14 02:10:44 -07:00
Jesse Cirimelli-Low c3da65c33c sky130 dp bank passing 2026-05-14 01:58:41 -07:00
Jesse Cirimelli-Low 5222224936 route supplies from endcaps to power ring 2026-05-13 16:45:52 -07:00
Jesse Cirimelli-Low afca50c20b power ring routing optimized, stretch crba pins to edge of power ring to avoid drc errors 2026-05-13 12:35:08 -07:00
Jesse Cirimelli-Low 34b317ce7d remove debug print statements 2026-05-11 16:05:20 -07:00
Jesse Cirimelli-Low 9fcf61f031 merge in array generation branch 2026-05-11 13:09:52 -07:00
Jesse Cirimelli-Low cbd2bd7c2e switch from conda to nix for tooling 2026-05-11 10:44:24 -07:00
Jesse Cirimelli-Low c864427734 make contacts perpendicular to power rails to avoid drc violations 2026-05-07 15:03:53 -07:00
Jesse Cirimelli-Low c3987f2537 change power ring spacing from magic numbers to drc based 2026-05-07 14:18:58 -07:00
Jesse Cirimelli-Low e7829cf641 allow tech file to specify connection to power rail per net 2026-05-06 10:42:02 -07:00
Jesse Cirimelli-Low 541d4ff572 parameterize how power ring is connected to crba 2026-05-06 09:50:56 -07:00
Jesse Cirimelli-Low e4a895ecb0 fix verbosity level 2026-04-30 13:02:03 -07:00
Jesse Cirimelli-Low a5c879f510 Merge remote-tracking branch 'openram_local/array_gen' into merge/full-array-gen-into-dev 
# Conflicts:
#	technology/sky130/custom/sky130_col_cap_array.py
 2026-04-30 12:43:19 -07:00
Jesse Cirimelli-Low ddac4254ec switch from conda to nix for tooling 2026-04-30 12:00:56 -07:00
Jesse Cirimelli-Low 88241ca685 add fix for cypress sp wls 2026-04-28 17:19:54 -07:00
Jesse Cirimelli-Low 5077282180 count wordlines from bottom going up 2026-04-28 14:04:42 -07:00
Jesse Cirimelli-Low c7f3ac33cd sky130 cypress dp working with offset relative to crba 2026-04-27 17:24:13 -07:00
Jesse Cirimelli-Low 3e569feebf Merge branch 'dev' into array_gen 2026-04-22 01:38:59 -07:00
Jesse Cirimelli-Low cb7f117daa squash commits 2026-04-22 01:33:47 -07:00
Gabriel Wicki 5cd43442b8 compiler: gdsMill: Modernize codebase. 
* compiler/gdsMill/pyx/graph/axis/tick.py: Modernize.
 2026-04-17 13:14:03 +02:00
Jesse Cirimelli-Low 515591a422 dual port rba lvs clean again with cell library changes 2026-04-14 14:48:26 -07:00
Matthew Guthaus 9274fbd4f2 Merge branch 'stable' into dev 2026-04-08 11:26:03 -07:00
Matthew Guthaus 449781d239 Revert "Revert "Update defunct code"" 
This reverts commit d142b906ee.
 2026-04-08 11:25:48 -07:00
Matt Guthaus d142b906ee
Revert "Update defunct code" 2026-04-08 11:19:03 -07:00
Gabriel Wicki e01e6a567d compiler: gdsMill: Modernize codebase. 
The few Python 2 statements are replaced with their modern
counterparts.  These are one of the following:
 - print() function calls (instead of statements),
 - Exception and Error raising,
 - passing/receiving tuples as function/lambda arguments,
 - the L suffix for numeral constants.

* compiler/gdsMill/pyx/box.py,
  compiler/gdsMill/pyx/connector.py,
  compiler/gdsMill/pyx/deformer.py,
  compiler/gdsMill/pyx/dvifile.py,
  compiler/gdsMill/pyx/epsfile.py,
  compiler/gdsMill/pyx/font/afm.py,
  compiler/gdsMill/pyx/font/t1font.py,
  compiler/gdsMill/pyx/graph/axis/texter.py,
  compiler/gdsMill/pyx/graph/axis/tick.py,
  compiler/gdsMill/sram_examples/cell6tDemo.py,
  compiler/gdsMill/sram_examples/newcell.py: Modernize syntax.
 2026-03-31 22:44:21 +02:00
Gabriel Wicki 26e11044db compiler: multibank: Fix syntax error. 
* compiler/modules/multibank.py (multibank) [compute_sizes]: Fix
syntax error.
 2026-03-31 22:28:10 +02:00
Jesse Cirimelli-Low b6d98c44d5 singleport cba passing on both tech files 2026-03-17 14:50:43 -07:00
Jesse Cirimelli-Low ffcbd51019 technology switching working 2026-03-17 11:44:20 -07:00
Jesse Cirimelli-Low ab33017fe2
Merge pull request #282 from ruhai-lin/stable 
Attempt to fix LVS mismatch and SRAM creation with banks for sky130
 2026-03-12 10:47:23 -07:00
rlin50 6d14626a75 Fix address bit ordering in sky130 1rw characterization 2026-02-23 15:32:08 -08:00
Maarten Boersma 7382ea7dda
fix #279: expliticly extract single number from numpy array to meet stricter numpy>=2.4.0 code hygiene 2026-01-16 15:05:28 +01:00
Jesse Cirimelli-Low 53d53ec271 checkpoint from tt submission 2026-01-14 12:08:26 -08:00
Jesse Cirimelli-Low 5a74605117 single port fixes 2025-09-12 11:25:03 -07:00
Jesse Cirimelli-Low 4ce6e0538b fix col_cap array for dummu compatability ...bitcells next 2025-03-06 02:05:43 -08:00
Jesse Cirimelli-Low f3c1c5fbb2 Merge branch 'singleport_refactor' into array_gen 2025-02-24 23:26:28 -08:00
mrg bc1cc36ade Merge branch 'whitespace_fix' of github.com:TristanRobitaille/OpenRAM into dev 2024-11-12 09:49:00 -08:00
Tristan Robitaille 1f5fe62456 Added whitespace between : and 'minimum_period', '1kOhm' and 'min_pulse_width' as required by Liberty file standard 2024-11-10 14:31:52 +01:00
mole99 85e242fa27 Add gf180mcu ROM example 2024-02-03 11:31:58 +01:00
Eren Dogan 0cf60a6a18 Give u+x permissions for rom tests 2024-01-20 17:49:52 -08:00
Eren Dogan 55e5c425e9 Fix same file error and enable passing tests 2024-01-20 08:38:18 -08:00
Eren Dogan 14c219d9f1 Enable working tests from disabled stamps 2024-01-19 15:16:30 -08:00
Eren Dogan 855139bc4e Add Makefile target to run broken tests only 2024-01-19 15:15:52 -08:00
Eren Dogan 0a1de57cae Update copyright year 2024-01-03 14:32:44 -08:00
mole99 8032fa75a4 Add LEF output for ROM 2023-12-21 08:07:49 +01:00
Hadir Khan 9d6052b86c fix for matching the layout vs verilog port names for rom 2023-12-20 15:30:07 -08:00
Eren Dogan efd43c3191 Merge branch 'dev' into issue_fix 2023-12-06 13:30:22 -08:00
Eren Dogan 7531e38cad Remove unused local variable 2023-12-05 11:18:58 -08:00
Eren Dogan 39a66fcb87 Fix some lint errors 2023-12-05 11:16:22 -08:00
Eren Dogan 6cfb22959c Remove unused imports 2023-12-05 11:08:32 -08:00