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OpenRAM
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2678 Commits

Author SHA1 Message Date
mrg c472a94f1e Rework bitcells. 
Name them 1port and 2port consistently.
Allow cell overrides to cell_1rw and cell_2rw or other.
Will use 2rw for 1rw/1r, 2rw, 1w/1r, etc.
 2020-11-13 10:07:40 -08:00
mrg 3567a3e913 Remove 1rw_1r 2020-11-13 08:10:16 -08:00
mrg cf63499e76 Convert bitcells to 1port and 2port 2020-11-13 08:09:21 -08:00
mrg 198c0faf85 Remove special s8 6t names 2020-11-13 07:45:31 -08:00
mrg 662d4ea724 Merge remote-tracking branch 'private/drclvs' into dev 2020-11-12 16:01:07 -08:00
mrg e6a7ecae84 Fix missing default path in pex 2020-11-12 14:43:57 -08:00
mrg 9eeab14639 Add comment before pininfo 2020-11-12 14:33:42 -08:00
mrg bdda7c4f5f Add bl/br pins to dummy array 2020-11-12 12:38:09 -08:00
mrg 190234df58 Add PININFO to outputs too 2020-11-12 12:12:53 -08:00
mrg 63941a10e1 Add None as sp_file parameter to local_drc_check 2020-11-12 10:01:38 -08:00
mrg d4c4658c77 Clean up invalid routing layer error message 2020-11-12 09:43:08 -08:00
mrg d3cb22c8c1 Fix pin vs module names issue #26 2020-11-12 09:33:48 -08:00
mrg 537e862d48 Add -full to LVS script 2020-11-10 20:38:41 -08:00
mrg 03dad01e4c Use readspice to define ports from sp netlist in Magic extract. 2020-11-10 17:06:24 -08:00
mrg 31ae56ff39 Simplify to a single DRC/LVS library test. 2020-11-10 16:45:00 -08:00
mrg 56c2222c2b Temp comment Magic GDS filter code. 2020-11-10 13:37:18 -08:00
mrg 57e708a6e1 Add 200 cycles. Can be commented out or run for shorter. 2020-11-09 15:20:36 -08:00
mrg 2c203530ad Merge branch 'drclvs' into dev 2020-11-09 14:36:36 -08:00
mrg 0ba2feee53 Fix errors in new run_sim calls and corners 2020-11-09 13:59:46 -08:00
mrg e31cbeaa6f Don't check for file to determine if it is included. 2020-11-09 12:11:47 -08:00
mrg 532492d5ae Output functional stimulus to output directory. 2020-11-09 12:00:25 -08:00
mrg 31d21e169f Skip LEF test as correct output keeps changing. 2020-11-09 11:14:55 -08:00
mrg 10542d6cc3 Output DRC and LVS run files to output directory. 2020-11-09 11:12:31 -08:00
mrg 66633a843b Add PDK layer names to tech file 2020-11-09 09:10:43 -08:00
mrg 2da9c307db Disable 4x16 decoder test for now 2020-11-06 13:50:04 -08:00
mrg 147649e142 Why was single port decoder test a dual port? 2020-11-06 12:21:30 -08:00
mrg 493c9125f1 Read different modules overrides for different num ports 2020-11-06 11:09:50 -08:00
mrg 8be1436d51 Use OPTS.bitcell everywhere 2020-11-05 16:55:08 -08:00
mrg 18d2987805 Cleanup 2020-11-05 16:30:15 -08:00
mrg a40716dd48 Cleanup imports 2020-11-05 14:32:08 -08:00
mrg 0118b73eec Cleanup imports 2020-11-05 14:31:53 -08:00
mrg 681b3a91aa Drop to debug in debug module when -d 2020-11-05 13:20:54 -08:00
mrg 2c76a2680f Adjust openram options. 
Remove option -d (dontpurge) and replace with keeptemp
Add option -d (debug) to drop into pdb.
Add option -k (--keeptemp) to keep temp files
 2020-11-05 13:12:26 -08:00
mrg a52aac5f31 Add gds flatten option for Magic 2020-11-05 13:12:08 -08:00
mrg ce7be7466f Model as subckt for Magic too 2020-11-05 13:11:36 -08:00
mrg b160c4a35d Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-11-04 14:31:42 -08:00
mrg 9a38f7a5f4 Enable gds readonly in Magic DRC/LVS 2020-11-04 10:50:53 -08:00
mrg fb0b285652 Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev 2020-11-04 10:40:20 -08:00
mrg 6e12d4d46c Skip tri gate array test 2020-11-04 06:57:51 -08:00
Matt Guthaus 844b850b74 Fix typo in 1w_1r bitcell 2020-11-03 17:14:45 -08:00
mrg 3315fe32ba Improve nominal corner message 2020-11-03 16:49:49 -08:00
mrg 45cdecdea9 Improve error message about missing DRC/LVS tools. 2020-11-03 15:47:04 -08:00
mrg 6335bc3784 Do not drop to pdb shell when verbose 2020-11-03 15:46:46 -08:00
mrg 29f4ee492b Fix missing imports in replica bitcells. 2020-11-03 15:24:44 -08:00
mrg 2f12c77668 Create single port memory config examples. 2020-11-03 14:42:56 -08:00
mrg fb9956fe96 Fix missing include 2020-11-03 13:50:45 -08:00
mrg d209e8d9a3 Disable perimeter pins for now 2020-11-03 13:35:34 -08:00
mrg 1de545fc8e Fix row and col cap custom names by adding default. 2020-11-03 13:32:15 -08:00
mrg 29ac541b28 Refactor dynamic cell name to utilize base class 2020-11-03 13:18:46 -08:00
mrg a128e0501e Use cell_name in col and row caps too. 2020-11-03 12:10:18 -08:00