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OpenRAM
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101 Commits

Author SHA1 Message Date
Aditi Sinha d5041afebc Merge branch 'dev' into bisr 2020-06-07 16:27:25 +00:00
mrg 717188f85c Change L shape of rbl route 2020-06-04 11:03:39 -07:00
Aditi Sinha eb0c595dbe SRAM layout and functional tests with spare cols 2020-06-03 12:31:30 +00:00
Aditi Sinha c7d86b21ae Spare cols with wmask enabled 2020-05-16 10:09:03 +00:00
Aditi Sinha 8bd1052fc2 Spare columns in full sram layout 2020-05-14 10:30:29 +00:00
Aditi Sinha a5c211bd90 Merge branch 'dev' into bisr 2020-05-13 22:39:29 +00:00
mrg b7c66d7e07 Changes to simplify metal preferred directions and pitches. 
Changes to allow decoder height to be a 2x multiple of bitcell height.
Split of control logic tests.
Fixed track spacing in SRAM and channel router
PEP8 cleanup.
 2020-05-10 11:32:45 -07:00
Aditi Sinha 2498ff07ea Merge branch 'dev' into bisr 2020-05-02 07:48:35 +00:00
Aditi Sinha 2661a42726 changes to support spare columns 2020-04-14 03:09:10 +00:00
mrg c8c74e8b69 Fix lvs_write in sram class 2020-04-06 15:20:59 -07:00
mrg f358de78bb Add optional lvs_lib netlists for LVS usage (sp_lib is for simulation) 2020-04-03 13:39:54 -07:00
mrg 2850b9efb5 Don't force check in lib characterization. PEP8 formatting. 2020-04-02 12:52:42 -07:00
mrg 9106e22b58 Fix typo and syntax error. 2020-04-02 10:37:21 -07:00
mrg 5349323acd PEP8 cleanup. DRC/LVS returns errors. 2020-04-02 09:47:39 -07:00
Aditi Sinha b75eeb7688 Merge branch 'dev' into bisr 2020-03-22 21:58:04 +00:00
Aditi Sinha a5afbfe0aa Fixed errors in extra rows characterization 2020-03-22 20:54:49 +00:00
mrg ee18f61cbf Route RBL to edge of bank. 2020-03-06 09:03:52 -08:00
mrg 05f9e809b4 PEP8 Formatting 2020-03-05 16:27:35 -08:00
mrg 6506622dfb PEP8 Formatting 2020-03-05 16:20:21 -08:00
mrg 5b23653369 PEP8 Formatting 2020-03-05 16:13:49 -08:00
Aditi Sinha 34939ebd70 Merge branch 'dev' into bisr 2020-02-20 17:09:09 +00:00
mrg 5928a93772 Merge branch 'dev' into tech_migration 2020-02-10 22:42:50 +00:00
jcirimel b212b3e85a s8 gdsless netlist only working up to dff array 2020-02-09 21:37:09 -08:00
mrg 4d85640a00 Change col addr spacing to col addr size 2020-02-07 22:20:16 +00:00
mrg 2ff058f5d5 PEP8 Cleanup and reverse pitch offset of col addr routing 2020-02-06 22:59:30 +00:00
mrg 4b06ab9eaf Move port 2 column address bus down. 
PEP 8 cleanup.
 2020-02-06 19:46:10 +00:00
Jesse Cirimelli-Low b107934672 fix styling 2020-02-06 12:15:52 +00:00
Jesse Cirimelli-Low 3a06141030 add simple sram sizing for netlist only 2020-02-06 12:10:49 +00:00
mrg 79391b84da Cleanup and rename vias. 2020-01-30 01:45:33 +00:00
Bastian Koppelmann 9749c522d1 tech: Make power_grid configurable 
this is the first step to allow engineers, porting technologies, more room
for routing their handmade cells.

For now, we don't allow the specification of power_grids where the lower layer
prefers to be routed vertically. This is due to the router not
connecting some pins properly in that case.

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2020-01-28 12:06:34 +01:00
Bastian Koppelmann fab963701b sram_base: Instantiate "dff_array" and "bank" through sram_factory 
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
 2019-12-18 17:33:50 +01:00
Matt Guthaus ed28b4983b Clean up and generalize layer rules. 
Convert metalN to mN.
Generalize helper constants in modules for
space, width, enclose, etc.
Use layer stacks whever possible.
Try to remove drc() calls in liu of helper constants.
 2019-12-17 11:03:36 -08:00
Matt Guthaus e143a6033f Use layer stacks from tech file in design class and throughout 2019-12-13 14:13:41 -08:00
Aditi Sinha 5b3846e1e5 Changed replica bitcell array to work with bank tests for non power of two rows 2019-12-08 13:24:39 +00:00
Matthew Guthaus aca99b87bc Fix config for tests 30 2019-11-16 22:22:30 +00:00
jsowash 8c33749223 Uncommented offset_all_coordinates. 2019-09-04 16:41:27 -07:00
jsowash febc053587 Moved SRAM macro in LEF file to origin and removed poly. 2019-09-04 16:11:12 -07:00
jsowash fbecb9bc02 Added poly to LEF files. 2019-09-04 14:06:17 -07:00
jsowash d6e7047e2f Added metal4 to lef files since it's now used with a wmask. 2019-09-04 13:04:51 -07:00
jsowash 4c40804b8f Moved via in write driver up for 2 port. 2019-09-03 15:14:41 -07:00
jsowash dd67490823 Changed routing to allow for 2 write port with write mask. 2019-09-03 14:43:03 -07:00
Matt Guthaus 69c5608b53 Allow gds to be written with supplies off. Fix extraction bug with new options. 2019-09-03 11:23:35 -07:00
jsowash e3b42430bd Changed max_gap_size_wmask to take into account column ffs. 2019-08-29 17:09:17 -07:00
jsowash bbe235074c Added max gap size for wmask and edited max gap size for data ff's to take into account m3 spacing. 2019-08-29 16:41:58 -07:00
jsowash 37116ce9d8 Increased spacing between wmask and data dffs. 2019-08-29 16:00:50 -07:00
jsowash c1906ade3f Removed A pin's via connection since it's created in the SRAM level and rearranged the SRAM flip flop creation. 2019-08-29 14:48:13 -07:00
jsowash af3d2af0ec Merge branch 'dev' into add_wmask 2019-08-29 12:56:11 -07:00
jsowash f13c8eae8d Moved column mux ff's to be horizontal with wmask flip flops and adjusted wmask AND array en pin location starting point. 2019-08-29 11:07:42 -07:00
Matt Guthaus 64fc771fc4 Simplify is not None 2019-08-22 15:02:52 -07:00
Matt Guthaus ee2456f433 Merge branch 'add_wmask' into dev 2019-08-22 15:01:41 -07:00