 Jesse Cirimelli-Low
|
0008df0204
|
catch where strap size is zero
|
2021-06-18 15:24:24 -07:00 |
|
|
Jesse Cirimelli-Low
|
2eb98083d0
|
Merge branch 'dev' into laptop_checkpoint
|
2021-06-18 14:21:39 -07:00 |
|
|
Jesse Cirimelli-Low
|
8ceece2af6
|
check for valid dimensions instead of recalcuating
|
2021-06-18 14:21:02 -07:00 |
|
 mrg
|
693a81fa8d
|
Fix spare_wen IO pin names
|
2021-06-18 10:44:35 -07:00 |
|
|
mrg
|
1299989332
|
Fix single spare_wen naming
|
2021-06-18 08:43:21 -07:00 |
|
|
mrg
|
67877175b2
|
Fix error in no spare column verilog
|
2021-06-18 08:41:26 -07:00 |
|
|
mrg
|
81d20ec2aa
|
Add spare cols to behavioral Verilog model
|
2021-06-18 07:23:41 -07:00 |
|
|
Jesse Cirimelli-Low
|
7b7c72706a
|
merge in dev
|
2021-06-17 09:49:32 -07:00 |
|
|
Jesse Cirimelli-Low
|
d9afe89770
|
remove print statement
|
2021-06-17 03:23:46 -07:00 |
|
|
Jesse Cirimelli-Low
|
1ce6b4d41a
|
fix freepdk45
|
2021-06-17 03:21:01 -07:00 |
|
 Hunter Nichols
|
131ff8bcef
|
Changed the regression test to only run models for the output being tested.
|
2021-06-16 23:50:20 -07:00 |
|
|
mrg
|
afe0902547
|
Enable small short func tests
|
2021-06-16 19:13:50 -07:00 |
|
|
mrg
|
b7f1c8e8fc
|
Fix name for detecting single port
|
2021-06-16 19:07:56 -07:00 |
|
|
mrg
|
c7c319c11f
|
Use extra bitcell version tag only for single port in sky130
|
2021-06-16 19:06:12 -07:00 |
|
|
mrg
|
d119a0e7ff
|
Use sky130 bitcell in simulation for BLs
|
2021-06-16 18:45:53 -07:00 |
|
|
mrg
|
1e486cd344
|
Use local spacing rule
|
2021-06-16 18:41:39 -07:00 |
|
|
Hunter Nichols
|
16e658726e
|
When determining bitline names, added a technology check for sky130.
|
2021-06-16 17:04:02 -07:00 |
|
|
Jesse Cirimelli-Low
|
e775f7a355
|
fixed indent
|
2021-06-16 12:36:00 -07:00 |
|
|
Jesse Cirimelli-Low
|
2b9df2ff1f
|
uncomment function sim and datasheet generation
|
2021-06-16 11:23:27 -07:00 |
|
|
mrg
|
6ac082ce23
|
Only replace simulator if it is defined.
|
2021-06-16 10:44:13 -07:00 |
|
|
mrg
|
1adada9e27
|
Merge branch 'dev' into xyce
|
2021-06-16 09:52:17 -07:00 |
|
|
Jesse Cirimelli-Low
|
25bc178132
|
extend input rail
|
2021-06-14 15:13:17 -07:00 |
|
|
Hunter Nichols
|
4132decd32
|
Merge branch 'dev' into automated_analytical_model
|
2021-06-14 14:45:48 -07:00 |
|
|
Hunter Nichols
|
74b55ea83b
|
Added a graph exclusion clear for the mux to prevent previous graph creations causing bugs.
|
2021-06-14 14:39:54 -07:00 |
|
|
Hunter Nichols
|
7df36a916b
|
Added an exclusion for unused column mux paths to prevent multiple outputs paths in graph.
|
2021-06-14 13:51:52 -07:00 |
|
|
Hunter Nichols
|
4d22201055
|
Changed name of regression test since we currently only test the delay.
|
2021-06-14 10:57:20 -07:00 |
|
|
mrg
|
159d0ed603
|
Fix s_en spacing problem.
|
2021-06-13 15:08:05 -07:00 |
|
|
mrg
|
53107a8322
|
Add ring test
|
2021-06-13 15:03:41 -07:00 |
|
|
mrg
|
d6a72aed37
|
Add 2x1 perimter pins to satisfy minimum area rule.
|
2021-06-13 15:00:46 -07:00 |
|
|
mrg
|
2e23fffadd
|
Fix comment
|
2021-06-13 14:18:55 -07:00 |
|
|
Jesse Cirimelli-Low
|
73cc6b3891
|
uncomment 4x16 decoder
|
2021-06-11 18:20:36 -07:00 |
|
|
Jesse Cirimelli-Low
|
bee9b07516
|
fix decoder routing
|
2021-06-11 18:19:07 -07:00 |
|
|
Jesse Cirimelli-Low
|
2e72da0e53
|
rotate input to rail contacts for drc
|
2021-06-10 14:01:28 -07:00 |
|
|
Jesse Cirimelli-Low
|
247a388ab5
|
Merge branch 'dev' into laptop_checkpoint
|
2021-06-09 18:25:45 -07:00 |
|
|
Jesse Cirimelli-Low
|
10f561648f
|
remove hierarchical decoder vertial m1 above pins
|
2021-06-09 18:24:21 -07:00 |
|
|
mrg
|
8964abc2b7
|
Change simulator based on one in use.
|
2021-06-09 16:02:32 -07:00 |
|
|
Hunter Nichols
|
4ec2e1240f
|
Merge branch 'dev' into automated_analytical_model
|
2021-06-09 15:45:41 -07:00 |
|
|
Hunter Nichols
|
c50ffe70b3
|
Added more configs for model and respective data.
|
2021-06-09 15:42:15 -07:00 |
|
|
Hunter Nichols
|
ccf98ad5a6
|
Added accuracy check in regression model test.
|
2021-06-09 13:44:42 -07:00 |
|
|
Hunter Nichols
|
b6b20c1f43
|
Removed level 0 debug statements for bitlines naming.
|
2021-06-09 12:53:31 -07:00 |
|
|
Hunter Nichols
|
f25dcf1b63
|
Fixed issue with bitline name warning occuring when no issue is present.
|
2021-06-09 12:52:26 -07:00 |
|
|
Hunter Nichols
|
a73bfe6c2c
|
Added more configs for model and data from scn4m_subm run.
|
2021-06-09 10:35:58 -07:00 |
|
|
mrg
|
a1cb20878d
|
Swap LH/HL hold times in sky130.
|
2021-06-08 11:14:27 -07:00 |
|
|
Hunter Nichols
|
3d82718f5a
|
Changed neural network model to be sklearn based
|
2021-06-07 12:26:45 -07:00 |
|
|
mrg
|
27c6a13923
|
Back out drc listall count for detecting errors
|
2021-06-04 15:51:50 -07:00 |
|
|
mrg
|
cf61096936
|
Merge branch 'laptop_checkpoint' into dev
|
2021-06-04 15:22:37 -07:00 |
|
|
Hunter Nichols
|
331e6f8dd5
|
Added functions for testing accuracy of current regression model and associated test.
|
2021-06-04 15:04:52 -07:00 |
|
|
Hunter Nichols
|
84783bbac5
|
Added more configs for model generation
|
2021-06-04 13:38:17 -07:00 |
|
|
Hunter Nichols
|
54639bbb94
|
Added more data for regression models
|
2021-06-04 13:37:21 -07:00 |
|
|
mrg
|
6643759345
|
Add back drc listall with correct output.
|
2021-06-04 11:06:39 -07:00 |
|