 Hunter Nichols
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a0921b4afc
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Merge branch 'dev' into automated_analytical_model
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2021-06-22 01:39:38 -07:00 |
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 mrg
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58f8c66020
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Fix disconnected spare_wen_0_0
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2021-06-21 17:36:20 -07:00 |
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Hunter Nichols
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294ccf602e
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Merged with dev, addressed conflict in port data
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2021-06-21 17:23:32 -07:00 |
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mrg
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bb1ac1a38e
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Fix incorrect bus indexing of spare_wen. Convert internal signals to not use braces.
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2021-06-21 15:23:08 -07:00 |
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mrg
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f3f19aeeeb
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Remove print statement
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2021-06-21 15:16:36 -07:00 |
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mrg
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1ce5823df8
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2021-06-21 13:14:23 -07:00 |
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 Jesse Cirimelli-Low
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56dc83de47
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fix typo
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2021-06-18 18:10:12 -07:00 |
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Jesse Cirimelli-Low
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2dbe928c09
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fix typo
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2021-06-18 18:08:57 -07:00 |
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Jesse Cirimelli-Low
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4688988434
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only check dimensions on single port
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2021-06-18 17:46:39 -07:00 |
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Jesse Cirimelli-Low
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2eb98083d0
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Merge branch 'dev' into laptop_checkpoint
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2021-06-18 14:21:39 -07:00 |
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Jesse Cirimelli-Low
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8ceece2af6
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check for valid dimensions instead of recalcuating
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2021-06-18 14:21:02 -07:00 |
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mrg
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693a81fa8d
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Fix spare_wen IO pin names
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2021-06-18 10:44:35 -07:00 |
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mrg
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1299989332
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Fix single spare_wen naming
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2021-06-18 08:43:21 -07:00 |
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Jesse Cirimelli-Low
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7b7c72706a
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merge in dev
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2021-06-17 09:49:32 -07:00 |
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Jesse Cirimelli-Low
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e775f7a355
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fixed indent
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2021-06-16 12:36:00 -07:00 |
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Jesse Cirimelli-Low
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2b9df2ff1f
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uncomment function sim and datasheet generation
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2021-06-16 11:23:27 -07:00 |
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Hunter Nichols
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4132decd32
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Merge branch 'dev' into automated_analytical_model
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2021-06-14 14:45:48 -07:00 |
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Hunter Nichols
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74b55ea83b
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Added a graph exclusion clear for the mux to prevent previous graph creations causing bugs.
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2021-06-14 14:39:54 -07:00 |
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Hunter Nichols
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7df36a916b
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Added an exclusion for unused column mux paths to prevent multiple outputs paths in graph.
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2021-06-14 13:51:52 -07:00 |
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mrg
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159d0ed603
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Fix s_en spacing problem.
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2021-06-13 15:08:05 -07:00 |
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mrg
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cf61096936
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Merge branch 'laptop_checkpoint' into dev
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2021-06-04 15:22:37 -07:00 |
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mrg
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cc4c6e909b
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Check if s_en exists before using it
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2021-06-04 07:48:26 -07:00 |
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mrg
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4107c983e2
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Make sure channel route is below s_en
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2021-06-04 07:14:49 -07:00 |
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Jesse Cirimelli-Low
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6705f99855
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merge in dev
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2021-05-28 14:06:23 -07:00 |
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mrg
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77f221d859
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Separate supply pin type from route supplies option
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2021-05-28 11:55:50 -07:00 |
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mrg
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f6587badad
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Improve supply routing for ring and side pins
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2021-05-28 10:58:30 -07:00 |
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Hunter Nichols
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b3bcf48d2e
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Merge branch 'dev' into automated_analytical_model
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2021-05-26 18:42:24 -07:00 |
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mrg
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8bf37ca708
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Connect dnwell taps to gnd
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2021-05-26 17:38:09 -07:00 |
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mrg
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7736d3b927
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Fix updated side pin option
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2021-05-26 16:14:46 -07:00 |
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mrg
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e611f66767
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Add dnwell
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2021-05-26 16:14:16 -07:00 |
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mrg
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cc91cdf008
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Add power ring pin
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2021-05-26 16:14:14 -07:00 |
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mrg
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7fa6c7ce0f
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Typo in wmask supply variable
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2021-05-26 15:24:31 -07:00 |
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mrg
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4a8e0cdabb
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Add top-level pin functionality
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2021-05-26 15:04:52 -07:00 |
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Hunter Nichols
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2f4f8ca912
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Fixed conflicts in delay and elmore modules on merge with dev.
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2021-05-25 15:25:43 -07:00 |
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mrg
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3abebe4068
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Add hierarchical seperator option to work with Xyce measurements.
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2021-05-14 16:16:25 -07:00 |
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Jesse Cirimelli-Low
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0ba229afe5
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Merge branch 'dev' into laptop_checkpoint
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2021-05-07 19:06:17 -07:00 |
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Jesse Cirimelli-Low
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e5662180e8
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single port 20 series tests running
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2021-05-07 18:44:45 -07:00 |
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mrg
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57c58ce4a5
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Always route data dff on m3 stack.
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2021-05-06 17:14:39 -07:00 |
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mrg
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f677c8a88d
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Fix predecoder offset after relocating bank offset
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2021-05-05 14:44:05 -07:00 |
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mrg
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b3948121df
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Default supply routing is tree.
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2021-05-05 14:04:24 -07:00 |
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mrg
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f48b0b8f41
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Add left stripe power routes to tree router as option.
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2021-05-05 13:45:12 -07:00 |
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mrg
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19ea33d43d
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Move delay line module down.
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2021-05-04 16:42:42 -07:00 |
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Jesse Cirimelli-Low
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a7d0a1ef3a
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remove breakpoint
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2021-05-03 16:54:54 -07:00 |
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Jesse Cirimelli-Low
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14e087a5eb
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offset bank coordinates
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2021-05-03 15:51:53 -07:00 |
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mrg
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a0e263b14a
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Add vdd/gnd pins to the side.
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2021-05-03 15:14:15 -07:00 |
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mrg
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f45efe3db6
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Abstracted LEF added. Params for array wordline layers.
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2021-04-21 11:04:01 -07:00 |
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Hunter Nichols
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5dad0f2c0e
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Merged with dev, fixed import conflict in lib
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2021-04-18 23:59:35 -07:00 |
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mrg
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a730fd0f10
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Use magic for LEF abstract. Fix supply perimter pin.
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2021-04-14 10:01:43 -07:00 |
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mrg
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e706f776eb
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Offset macro to 0,0 which was accidentally comented by a PR
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2021-04-13 16:24:13 -07:00 |
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mrg
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229b0059c4
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Add perimeter margin to expand pins outside perimeter for OpenRoad router.
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2021-04-07 16:08:29 -07:00 |
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