 mrg
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11a82b7283
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Fixed local bitcell array for single and dual port
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2020-08-27 14:03:05 -07:00 |
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mrg
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e92337ddaf
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Separate get_ and get_all for bitlines and wordlines
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2020-08-25 17:08:48 -07:00 |
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mrg
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28bd93bf51
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Still working on array refactor
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2020-08-25 11:50:44 -07:00 |
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mrg
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8dee5520e0
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Standardize array names independent of bitcell
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2020-08-21 13:44:35 -07:00 |
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mrg
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b762580ee2
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Skip global test for now
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2020-08-19 11:36:21 -07:00 |
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mrg
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224e359208
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Fix pin order for replica array
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2020-08-18 15:59:05 -07:00 |
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mrg
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f58fc6579f
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Rename local/global tests
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2020-08-18 15:58:44 -07:00 |
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mrg
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e3e4bac922
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Fix replica bitcell array for right only RBL
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2020-08-18 15:47:52 -07:00 |
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mrg
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59d65c46c3
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Fix bug in not adding RBLs in local bitcell array
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2020-08-18 15:11:10 -07:00 |
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mrg
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b288bba43e
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Add global bitcell array test
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2020-08-18 14:29:23 -07:00 |
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mrg
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99e252d6d4
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Update interface of RBL array
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2020-08-17 17:19:07 -07:00 |
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mrg
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b1e55f9072
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Add local bitcell array
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2020-08-17 15:14:42 -07:00 |
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mrg
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797c41c750
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Skip local bitcell array test
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2020-08-13 14:36:39 -07:00 |
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mrg
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8e890c2014
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Replica bitcell with all the fixings
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2020-08-11 15:00:29 -07:00 |
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mrg
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eef97ff215
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Reabstracting bit and word line names.
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2020-08-06 11:17:49 -07:00 |
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mrg
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2fa561f98f
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Local bitcell array edits. Skip test by default.
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2020-07-29 10:08:13 -07:00 |
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mrg
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c260297366
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Allow replica_bitcell_array without the replica columns for local wordlines.
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2020-07-27 16:22:21 -07:00 |
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mrg
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69cab42676
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Add pbuf_dec gate
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2020-07-27 13:59:55 -07:00 |
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mrg
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26b01e37c6
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Fix pbuf test info
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2020-07-27 13:59:35 -07:00 |
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mrg
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2991534d3f
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Drafting local bitline stuff.
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2020-07-23 17:15:39 -07:00 |
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mrg
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e1967dc548
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Draft local and global arrays. Ensure rows before cols in usage.
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2020-07-23 14:43:14 -07:00 |
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mrg
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3379f46da1
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Fail unit test, but mention if LVS passes and DRC fails.
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2020-06-30 16:22:44 -07:00 |
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mrg
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0a87691176
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Run Calibre LVS even if DRC fails.
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2020-06-30 15:27:10 -07:00 |
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mrg
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4e7e0c5954
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Skip test in sky130
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2020-06-29 15:28:16 -07:00 |
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mrg
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af4ed3dd6e
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Skip riscv func test for time sake
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2020-06-26 06:50:45 -07:00 |
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mrg
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76e5389c33
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Change riscv func test name
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2020-06-25 17:43:17 -07:00 |
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mrg
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9eb1b500ea
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Skip phys riscv test
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2020-06-25 17:31:23 -07:00 |
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mrg
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7220b23402
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Add riscv unit tests
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2020-06-25 15:34:18 -07:00 |
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mrg
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b3d1161957
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Add u+x permissions to new tests
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2020-06-24 08:19:25 -07:00 |
|
 Joey Kunzler
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22ed725a35
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made 1rw_1r tests for write driver and wmask, fixed typo in portdata_wmask_1rw_1r_test
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2020-06-23 18:16:14 -07:00 |
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mrg
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22c821f5d8
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Change port_address test to 256 for riscv
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2020-06-23 15:40:00 -07:00 |
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mrg
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1a528f9739
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Skip and4_dec test
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2020-06-23 10:08:28 -07:00 |
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mrg
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92fc30005c
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Use factory in and_dec tests
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2020-06-22 16:55:49 -07:00 |
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mrg
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5872f553e1
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Rename tests for consistency
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2020-06-19 08:53:35 -07:00 |
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mrg
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239b3ea007
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Make wmask test a 1rw/1r
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2020-06-19 08:49:48 -07:00 |
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mrg
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a862cf3cb2
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Test more single level col mux configs
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2020-06-15 10:17:54 -07:00 |
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mrg
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6c04166876
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Update port data wmask tests
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2020-06-15 06:05:05 -07:00 |
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mrg
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9930b5f3f6
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Do not run tapless unit tests
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2020-06-14 14:18:25 -07:00 |
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mrg
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33a32101c9
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DRC and LVS fixes for pinv_dec
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2020-06-12 15:23:51 -07:00 |
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mrg
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dff28a9997
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Merge branch 'tech_migration' into dev
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2020-06-10 17:09:05 -07:00 |
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mrg
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fdf92d0da1
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Rename test 14
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2020-06-10 16:41:26 -07:00 |
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mrg
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469cd260b9
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Change bitcell array name to match
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2020-06-10 14:54:20 -07:00 |
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mrg
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f2c45a230e
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Add new replica column test. Add more skip tests.
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2020-06-10 11:00:00 -07:00 |
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mrg
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10be2d08b5
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Full path to skip tests file
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2020-06-10 10:23:05 -07:00 |
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mrg
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c119e60e79
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Add more s8 skip tests
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2020-06-10 10:14:52 -07:00 |
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mrg
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d4fc88124a
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Rename dff_buf test
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2020-06-09 17:18:19 -07:00 |
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mrg
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14782914b3
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Remove vertical pand gates
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2020-06-09 16:40:59 -07:00 |
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mrg
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c6b875146d
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Use local skip file
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2020-06-09 16:33:59 -07:00 |
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mrg
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fd49d3ed6a
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Add tech specific skip tests for making new techs.
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2020-06-09 16:09:15 -07:00 |
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mrg
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580b0601b5
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Unskip 20_psram_1bank_4mux_1rw_1r_test
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2020-06-09 16:04:39 -07:00 |
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