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OpenRAM
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441 Commits

Author SHA1 Message Date
Matt Guthaus 63a8f7c653 Remove m2 from write driver 2018-04-16 16:15:35 -07:00
Matt Guthaus bb1ec63c4f Removed msf data flop from bank 2018-04-16 16:03:46 -07:00
Matt Guthaus 1ba87c88f5 Remove supply rails in decoder 2018-04-16 15:59:52 -07:00
Matt Guthaus 13adfc3724 Add bank ground routing 2018-04-16 10:15:36 -07:00
Matt Guthaus 3fe4578feb Change stages of delay to odd 2018-04-16 10:15:15 -07:00
Matt Guthaus 70c92c27ef Supply to M3 for bank select logic 2018-04-11 16:55:09 -07:00
Matt Guthaus 010a187545 Remove dead logic 2018-04-11 16:54:55 -07:00
Matt Guthaus e038561b4a Move supply to M3 in wordline driver 2018-04-11 16:23:45 -07:00
Matt Guthaus 6640d3491d Tri gate and array supply to M2 and M3 2018-04-11 15:11:47 -07:00
Matt Guthaus 1e36e8e20c Fix ms_flop array for M3 supplies 2018-04-11 14:25:04 -07:00
Matt Guthaus 873be38e15 Add M3 pins on dff_buf array 2018-04-11 12:09:15 -07:00
Matt Guthaus 4971dde316 Rename pin variable 2018-04-11 12:08:57 -07:00
Matt Guthaus fa59b3d33d Copy predecoder supply pins 2018-04-11 11:56:41 -07:00
Matt Guthaus 1afb0a1d86 Add M3 supply vias to decoder. 2018-04-11 11:47:37 -07:00
Matt Guthaus 3ba90c035f Don't bring M2 rails over supply to allow supply connections. 2018-04-11 11:47:22 -07:00
Matt Guthaus f3baf48c22 Rotate vias in hierarchical predecodes 2018-04-11 11:12:32 -07:00
Matt Guthaus 424eb17921 Add M3 pins to hierarchical predecodes 2018-04-11 11:10:34 -07:00
Matt Guthaus 4f8ab78ee2 Change write driver supply pins to M2 2018-04-11 09:29:54 -07:00
Matt Guthaus a6c2e77bcf Move precharge and column mux cells to pgate directory. 
Move gnd to M3 in column mux.
Create column mux cell unit test.
 2018-04-06 17:15:14 -07:00
Matt Guthaus 91e342e4c9 Move precharge vdd pin to left edge. 2018-04-04 15:03:29 -07:00
Matt Guthaus a772217172 Route precharge_array vdd in M3 2018-04-04 13:49:55 -07:00
Matt Guthaus f9916f9f43 Route precharge vdd to M3 2018-04-04 13:34:56 -07:00
Matt Guthaus 4c4cfb2a3c Add local dir for output. Will remove later. 2018-04-04 09:55:32 -07:00
Matt Guthaus a0bf5345f8 Mostly working for 1 bank. 2018-03-23 08:14:26 -07:00
Matt Guthaus 97c08bce95 Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control. 
Shift s_en buffers even with other cells.
 2018-03-23 08:14:09 -07:00
Matt Guthaus 696433b1ec Add bank_sel to bank_select module as input. 
Remove reference to control in sram.
Add dff_buf_array to options.
Added inverted DFF
Add variable height pinvbuf
 2018-03-23 08:13:39 -07:00
Matt Guthaus 5bf915a232 Detect via size for power ring. 2018-03-23 08:13:28 -07:00
Matt Guthaus ed2fa10caa Use LSB for column mux. 
Detect via size for power ring.
 2018-03-23 08:13:20 -07:00
Matt Guthaus bab92fcf38 Rework hierarchical decoder to not be folded. Remove address from central bank bus and access via side pins now. Eight way column mux now works. 2018-03-23 08:13:20 -07:00
Matt Guthaus 1f81b24e96 Single bank passing DRC and LVS again. 
Unfold hierarchical decoder to improve routability.
 2018-03-23 08:13:10 -07:00
Matt Guthaus b867e163a6 Move label pins to center like layout pins. 
Rework of control logic with vertical poly. Passes DRC/LVS.
Single bank passing DRC.
 2018-03-23 08:12:59 -07:00
Matt Guthaus 8ca9ba4244 Recreate delay chain and RBL to have vertical poly only. 2018-03-23 08:12:47 -07:00
Matt Guthaus ed8eaed54f Reworking control logic for veritcal poly. Rewrote delay line. Rewrote buffered-DFF array. 2018-03-23 08:12:47 -07:00
Matt Guthaus c020d74f26 Add dff_buf and dff_array modules. 2018-03-23 08:11:51 -07:00
Matt Guthaus a2514878c1 Simplify dff array names of 1-dimension. Add ports on metal2. 2018-03-05 16:22:35 -08:00
Matt Guthaus 1eda3aa131 Add back offset all coordinates in sram.py. 2018-03-05 14:22:24 -08:00
Matt Guthaus ba82222475 Add bank_select module option 2018-03-05 14:06:12 -08:00
Matt Guthaus 54f245cb9f Fix capitalization of pins in dff_array 2018-03-05 14:04:34 -08:00
Matt Guthaus 6e9437356a Fix LEF tests with new power supplies. 2018-03-05 13:55:02 -08:00
Matt Guthaus 4205a6a700 Connect bank supply rings in sram.py. 2018-03-05 13:49:22 -08:00
Matt Guthaus 0c203c1c7e RBL width is max of delay chain or bitcell load. 2018-03-05 10:23:13 -08:00
Matt Guthaus 98fb1173df Move bank select logic to a self contained module. 2018-03-05 10:22:51 -08:00
Matt Guthaus 0f721a3d40 Add vdd and gnd rails around bank structure. 2018-03-04 17:53:22 -08:00
Matt Guthaus 8d9b79dfd8 Add dff_buf for buffered flop arrays. 2018-03-04 16:13:10 -08:00
mguthaus 04ed3792c7 Fix analytical lib tests with new power numbers. 2018-03-02 18:13:06 -08:00
Matt Guthaus 242a1a68e0 Fix duplicate instance gds output bug that only showed up in Magic extraction. Every time we saved a GDS, additional instances were put in the GDS file. Most extraction tools ignored this, but Magic actually extracted duplicates. 2018-03-02 18:05:46 -08:00
Matt Guthaus 2b130de198 Rewrite run_lvs.sh script to utilize setup.tcl file. 2018-03-02 18:03:55 -08:00
Matt Guthaus 7293eb33bc Merge branch 'dev' of https://github.com/mguthaus/OpenRAM into dev 2018-03-02 10:30:16 -08:00
Hunter Nichols d0dcd9f34b Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality. 2018-03-01 23:34:15 -08:00
Hunter Nichols 93ad99b9e1 Changed variable names in analytical power function to be more clear. 2018-02-28 12:32:54 -08:00