 mrg
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5776788574
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Order of wordlines and bitlines in bank
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2020-08-18 16:30:38 -07:00 |
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mrg
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224e359208
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Fix pin order for replica array
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2020-08-18 15:59:05 -07:00 |
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mrg
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f58fc6579f
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Rename local/global tests
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2020-08-18 15:58:44 -07:00 |
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mrg
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e3e4bac922
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Fix replica bitcell array for right only RBL
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2020-08-18 15:47:52 -07:00 |
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mrg
|
59d65c46c3
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Fix bug in not adding RBLs in local bitcell array
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2020-08-18 15:11:10 -07:00 |
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mrg
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2643a96f97
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Order inputs wordline, bitline, supply
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2020-08-18 14:29:36 -07:00 |
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mrg
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b288bba43e
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Add global bitcell array test
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2020-08-18 14:29:23 -07:00 |
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mrg
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e37a9234cc
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Update replica column call to new refactor
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2020-08-18 09:14:50 -07:00 |
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mrg
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bc974ff78e
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Update replica column unit tests for new refactor
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2020-08-18 08:56:24 -07:00 |
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mrg
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99e252d6d4
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Update interface of RBL array
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2020-08-17 17:19:07 -07:00 |
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mrg
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b1e55f9072
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Add local bitcell array
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2020-08-17 15:14:42 -07:00 |
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mrg
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3a692e2846
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Comment updates
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2020-08-17 14:35:39 -07:00 |
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mrg
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60224b105f
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Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2020-08-17 14:20:34 -07:00 |
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mrg
|
94bfad4113
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Horizontal gnd vias for unused array inputs
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2020-08-17 13:24:34 -07:00 |
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mrg
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bddb251a84
|
More room for power contacts
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2020-08-17 12:32:44 -07:00 |
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mrg
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2c43d315db
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Revert gds readonly true
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2020-08-17 12:19:23 -07:00 |
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mrg
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35a1b00aa0
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Extra space for unused wl contacts
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2020-08-14 14:23:40 -07:00 |
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mrg
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170e3feb7d
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Fix order of replica wordlines and bitlines
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2020-08-14 14:14:49 -07:00 |
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mrg
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604e433e22
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Add readonly true for Magic scripts
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2020-08-14 10:40:31 -07:00 |
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mrg
|
dfb593e9b4
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Add draft lyt file -- connectivity not working
|
2020-08-14 10:38:22 -07:00 |
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mrg
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2ac04efe2e
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Must connect for replica cells other than top/bottom
|
2020-08-13 16:26:19 -07:00 |
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mrg
|
797c41c750
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Skip local bitcell array test
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2020-08-13 14:36:39 -07:00 |
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mrg
|
50525e70f4
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Fix up to SRAM level with new replica bitcell array ports.
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2020-08-13 14:29:10 -07:00 |
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mrg
|
8dbaa66aa5
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Merge branch 'super' into dev
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2020-08-12 14:25:13 -07:00 |
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mrg
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7ac4574e4f
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Use micron units for all simulation in sky130
|
2020-08-12 13:54:55 -07:00 |
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mrg
|
5fc6438553
|
Fix pinv_dec super call
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2020-08-12 13:22:28 -07:00 |
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mrg
|
15c8c200f3
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Undo super() in measurement abstract class
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2020-08-12 12:10:12 -07:00 |
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mrg
|
55814a8f74
|
Fix syntax errors in pgates for super edits
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2020-08-12 11:15:32 -07:00 |
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mrg
|
0bec6f0439
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Fix SRAM to use simulation spice instead of LVS spice
|
2020-08-12 10:41:21 -07:00 |
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mrg
|
a55909930f
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Replace replcia_bitcell_array with new one in bank
|
2020-08-12 09:49:14 -07:00 |
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mrg
|
8e890c2014
|
Replica bitcell with all the fixings
|
2020-08-11 15:00:29 -07:00 |
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mrg
|
30976df48f
|
Change inheritance inits to use super
|
2020-08-06 11:33:26 -07:00 |
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mrg
|
eef97ff215
|
Reabstracting bit and word line names.
|
2020-08-06 11:17:49 -07:00 |
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mrg
|
037de96989
|
Merge branch 'dev' into wlbuffer
|
2020-08-05 10:37:29 -07:00 |
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mrg
|
528cb07635
|
Merge branch 'dev' into wlbuffer
|
2020-08-05 10:01:43 -07:00 |
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|
Matt Guthaus
|
8ec10cacd7
|
Merge pull request #86 from bvhoof/dev
Dev
|
2020-08-03 10:19:10 -07:00 |
|
 Bob Vanhoof
|
9b8ef5ef57
|
fix: generated pex file was not passed correctly to lib characterizer
|
2020-08-03 10:16:12 +02:00 |
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|
Bob Vanhoof
|
487bb6c6e9
|
Merge branch 'dev' of github:VLSIDA/OpenRAM into CalibrePexFilesUpdate
|
2020-08-03 09:32:27 +02:00 |
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|
Bob Vanhoof
|
dc55ededc1
|
fix regession tests after calibre fix
|
2020-07-31 12:51:34 +02:00 |
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mrg
|
487027a9f2
|
Fix pex file names
|
2020-07-30 11:35:13 -07:00 |
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mrg
|
8fa0065aaf
|
Undo PR 82 changes -- broke unit test.
|
2020-07-30 11:09:19 -07:00 |
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mrg
|
a663d903c5
|
Merge branch 'dev' of github.com:VLSIDA/PrivateRAM into dev
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2020-07-30 08:44:25 -07:00 |
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|
Matt Guthaus
|
68387ec525
|
Merge pull request #84 from bvhoof/CalibrePexFilesUpdate
calibrepex: file copy fix
|
2020-07-30 08:40:35 -07:00 |
|
 Hunter Nichols
|
c6f2edc20d
|
Changed warning message for multiport analytical characterization.
|
2020-07-29 19:50:06 -07:00 |
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mrg
|
64d61f4d56
|
Merge remote-tracking branch 'private/dev' into dev
|
2020-07-29 12:16:41 -07:00 |
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|
mrg
|
f23d2e36a7
|
Don't obstruct control logic signals with dffs when no column mux.
|
2020-07-29 10:31:18 -07:00 |
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|
mrg
|
8a2fa90cd5
|
Merge remote-tracking branch 'private/dev' into dev
|
2020-07-29 10:11:26 -07:00 |
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|
mrg
|
2fa561f98f
|
Local bitcell array edits. Skip test by default.
|
2020-07-29 10:08:13 -07:00 |
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|
Hunter Nichols
|
b4dafac489
|
Fixed issue with sen measurement not being added
|
2020-07-27 23:55:03 -07:00 |
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|
mrg
|
c260297366
|
Allow replica_bitcell_array without the replica columns for local wordlines.
|
2020-07-27 16:22:21 -07:00 |
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