Marti Alonso
21868f9de7
Consider spare columns when building liberty file
...
Spare columns are considered as extra data bits, thus extra pins are
added. However, the data bus size on the liberty file only accounted for
the real data bits. This would cause pin size mismatch issues when using
such macros in OpenROAD and left the whole data port disconnected.
Fix it by properly setting the data bus size. Additionally, add the
spare_wen pins which were also missing.
2025-08-15 23:48:31 +00:00
Tristan Robitaille
1f5fe62456
Added whitespace between : and 'minimum_period', '1kOhm' and 'min_pulse_width' as required by Liberty file standard
2024-11-10 14:31:52 +01:00
Eren Dogan
0a1de57cae
Update copyright year
2024-01-03 14:32:44 -08:00
Bugra Onal
ed0c93ba55
Only add drc errors from compiler
2023-07-10 14:05:44 -07:00
Bugra Onal
9002a8ac70
Merge branch 'dev' into char
2023-02-14 15:05:27 -08:00
Bugra Onal
b70f919a2b
Characterize only nom corner
2023-02-14 12:01:14 -08:00
Eren Dogan
e5fc25da6f
Update copyright year
2023-01-28 22:56:27 -08:00
Eren Dogan
96e57507bf
Add copyright check to code format test
2022-11-30 14:50:43 -08:00
Eren Dogan
fccdc3c45b
Use library imports globally
2022-11-27 13:01:20 -08:00
Bugra Onal
dc1626879e
Characterizer wmask check for write_size
2022-08-10 16:11:19 -07:00
samuelkcrow
dfbf0ba6e1
Make git dependency visible and enforce it.
...
resolves #87
2021-10-04 14:43:14 -07:00
Hunter Nichols
39ae1270d7
Merge branch 'dev' into cacti_model
2021-09-20 17:01:50 -07:00
mrg
9694237dba
Flip MSB and LSB in lib file due to bug report
2021-07-28 08:12:33 -07:00
Hunter Nichols
ebc91814e5
Fixed various issues with imported code from CACTI, added CACTI as an option for analytical sim, added placeholder names in tech files for CACTI
2021-07-12 15:48:47 -07:00
Hunter Nichols
3d82718f5a
Changed neural network model to be sklearn based
2021-06-07 12:26:45 -07:00
Hunter Nichols
b3bcf48d2e
Merge branch 'dev' into automated_analytical_model
2021-05-26 18:42:24 -07:00
mrg
e16f44cc81
Update lib file with external supply names
2021-05-26 15:34:32 -07:00
Hunter Nichols
76f5578cc1
Removed path delays from characterization output to not disturb the current testing flow.
2021-05-25 15:19:27 -07:00
Hunter Nichols
23368c0fcf
Updated tests and elmore model with load_slew lists. Changed naming on characterization output to not clash with testing.
2021-05-25 14:49:28 -07:00
Hunter Nichols
0434e57609
Added target in makefile to run configs and store results in tech directory.
2021-05-17 14:03:32 -07:00
Hunter Nichols
16904496ac
Made path delays write out to the extended OPTS file.
2021-05-05 01:14:54 -07:00
Hunter Nichols
5dad0f2c0e
Merged with dev, fixed import conflict in lib
2021-04-18 23:59:35 -07:00
mrg
d609e4ea04
Reimplement trim options (except on unit tests).
...
Allow trim netlist to be used for delay and functional simulation.
Each class implements a "trim_insts" set of instances that can be removed.
By default far left, right, top and bottom cells in the bitcell arrays are kept.
Use lvs option in sp_write
Fix lvs option in sram.
2021-04-07 16:07:56 -07:00
Hunter Nichols
6f01ab4792
Added simulation time modeling to regression model.
2021-03-22 12:55:29 -07:00
Hunter Nichols
208586a8e8
Added simulation time in the datasheet
2021-03-22 12:21:10 -07:00
Hunter Nichols
b5516865f1
Added option to allow specific load/slew combinations in config file.
2021-02-24 16:43:34 -08:00
Hunter Nichols
c308dd34a4
Merge branch 'dev' into elmore_model_tuning
2021-02-15 14:50:56 -08:00
Hunter Nichols
f81c1ee4fc
Contents of previous datasheet truncated if paths are the same
2021-02-05 16:51:35 -08:00
Hunter Nichols
df8d59f32e
Merge branch 'dev' into automated_analytical_model
2021-02-01 01:49:45 -08:00
Matt Guthaus
30fc81a1f0
Update copyright year.
2021-01-22 11:23:28 -08:00
Hunter Nichols
e26e17c53f
Added option to specify exact corners for characterization in config file
2021-01-22 00:50:28 -08:00
Hunter Nichols
d1b240dfb5
Added nom_voltage, etc back but changed values to replicate the operating conditions. Readded nom values back in golden files.
2021-01-21 13:52:55 -08:00
Hunter Nichols
b0c2722583
Changed lib file to only contain reference to the operating voltage and removed nominal voltage references.
2021-01-19 15:22:50 -08:00
Hunter Nichols
ed3d39a1b8
Added updated model data with slews and loads. Changed linear regressions to account for additional models.
2021-01-13 13:04:34 -08:00
Hunter Nichols
d6d8a037f1
Added values to datasheet info which will be used for model training
2021-01-11 15:20:56 -08:00
Hunter Nichols
d8437249f7
Condensed some datasheet code in lib.py
2021-01-06 15:53:22 -08:00
Hunter Nichols
bb841fc84d
Added option to output the datasheet.info file.
2021-01-06 12:45:34 -08:00
Hunter Nichols
6eac0530a1
Added words per row to datasheet
2020-12-22 15:00:11 -08:00
Hunter Nichols
732404b330
Added an option that prevents lib.py from generating corners and only uses corners in config file.
2020-12-17 15:32:15 -08:00
Hunter Nichols
25544c3974
Added similar interface to linear regression as elmore
2020-12-14 13:59:31 -08:00
Hunter Nichols
0adcf8935f
Added linear regression model for power.
2020-12-09 15:31:43 -08:00
Hunter Nichols
fc55cd194d
Added model selection option.
2020-12-09 12:54:11 -08:00
Hunter Nichols
8a75b83889
Fixed input scaling bugs delay prediction model
2020-12-07 14:36:01 -08:00
Hunter Nichols
5f4a2f0231
Added function to get all data and scale vs just a portion
2020-12-07 13:11:04 -08:00
Hunter Nichols
dcd20a250a
Changed linear regression model to reference data in tech dir vs local ref.
2020-12-02 15:20:50 -08:00
Hunter Nichols
d111041385
Refactored analytical model to be it's own module with shared code moved to simulation
2020-12-02 14:06:39 -08:00
mrg
da721a677d
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
mrg
7da3653ce5
Only output wmask to lib file in w or rw ports.
2020-10-16 16:59:51 -07:00
mrg
35c91168f7
Add load/slew scale option to config files
2020-10-16 13:52:36 -07:00
mrg
2011974e01
Make drc and lvs errors a member variable. Run only once.
2020-07-13 12:49:24 -07:00