mirror of https://github.com/VLSIDA/OpenRAM.git
Changed lib file to only contain reference to the operating voltage and removed nominal voltage references.
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@ -224,10 +224,6 @@ class lib:
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self.lib.write(" slew_lower_threshold_pct_rise : 10.0 ;\n")
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self.lib.write(" slew_upper_threshold_pct_rise : 90.0 ;\n\n")
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self.lib.write(" nom_voltage : {};\n".format(tech.spice["nom_supply_voltage"]))
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self.lib.write(" nom_temperature : {};\n".format(tech.spice["nom_temperature"]))
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self.lib.write(" nom_process : {};\n".format(1.0))
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self.lib.write(" default_cell_leakage_power : 0.0 ;\n")
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self.lib.write(" default_leakage_power_density : 0.0 ;\n")
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self.lib.write(" default_input_pin_cap : 1.0 ;\n")
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@ -238,7 +234,7 @@ class lib:
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self.lib.write(" default_max_fanout : 4.0 ;\n")
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self.lib.write(" default_connection_class : universal ;\n\n")
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self.lib.write(" voltage_map ( VDD, {} );\n".format(tech.spice["nom_supply_voltage"]))
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self.lib.write(" voltage_map ( VDD, {} );\n".format(self.voltage))
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self.lib.write(" voltage_map ( GND, 0 );\n\n")
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def create_list(self,values):
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