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OpenRAM
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90 Commits

Author SHA1 Message Date
samuelkcrow 8793dda40a characterizer and functional simulator working from command line 2022-08-10 12:06:18 -07:00
mrg 2711093442 Improve signal debug output 2021-07-01 12:47:17 -07:00
mrg bbdc728ac5 Edits to functional simulation. 
Use correct .TRAN with max timestep.
Seed functional sim with a 3 writes to start for more read addresses.
Move formatting code to simulation module to share.
 2021-07-01 09:59:13 -07:00
mrg 1ae68637ee Utilize same format for output 2021-06-29 17:04:32 -07:00
mrg 91603e7e01 Fix spare+value notation error 2021-06-29 16:44:52 -07:00
mrg 927de3a240 Debugging then disabling spare cols functional sim for now. 2021-06-29 15:47:53 -07:00
mrg ee1c2054d3 Add formatted debug output 2021-06-29 11:26:49 -07:00
mrg c4aec6af8c Functional fixes. 
Off by one error of max address with redundant rows.
Select reads 3x more during functional sim.
 2021-06-29 09:33:44 -07:00
mrg 3abebe4068 Add hierarchical seperator option to work with Xyce measurements. 2021-05-14 16:16:25 -07:00
mrg 61b1b90dd3 Use built in binary conversion. Improve spare debug output. 2021-04-07 16:08:29 -07:00
mrg 5843aa037c Update functional test to use spare columns separately. 
Fix no spare columns data width error.
 2021-04-07 16:08:24 -07:00
mrg d609e4ea04 Reimplement trim options (except on unit tests). 
Allow trim netlist to be used for delay and functional simulation.
Each class implements a "trim_insts" set of instances that can be removed.
By default far left, right, top and bottom cells in the bitcell arrays are kept.

Use lvs option in sp_write

Fix lvs option in sram.
 2021-04-07 16:07:56 -07:00
mrg 014c95f761 Add accounting output to ngspice 2021-04-01 16:48:15 -07:00
mrg c7f99aef2c Add functional comment to aid debugging checks. 2021-03-31 12:14:20 -07:00
Matt Guthaus 30fc81a1f0 Update copyright year. 2021-01-22 11:23:28 -08:00
mrg 532492d5ae Output functional stimulus to output directory. 2020-11-09 12:00:25 -08:00
mrg da721a677d Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
mrg 1e24b780bb Initial pex sram test. 2020-10-02 13:32:52 -07:00
Matt Guthaus 2b475670f7 Check for failed result in functional simulation 2020-09-30 12:40:07 -07:00
mrg bca69b24e3 Optional number of functional cycles 2020-09-29 13:43:54 -07:00
mrg 0c280e062a Fix func test with row/col of 0. PEP8 cleanup. Smaller global test case. 2020-09-29 11:35:58 -07:00
mrg d7e2340e62 Lots of PEP8 cleanup. Refactor path graph to simulation class. 2020-09-29 10:26:31 -07:00
mrg 88731ccd8e Fix rounding error for wmask with various word_size 2020-09-28 09:53:01 -07:00
Hunter Nichols 500327d59b Fixed import in simulation and fixed names in functional 2020-09-04 02:24:18 -07:00
Hunter Nichols d027632bdc Moved majority of code duplicated between delay and functional to simulation 2020-09-02 14:22:18 -07:00
mrg 30976df48f Change inheritance inits to use super 2020-08-06 11:33:26 -07:00
mrg 403ea17039 PEP8 formatting 2020-06-18 14:55:01 -07:00
Aditi Sinha eb0c595dbe SRAM layout and functional tests with spare cols 2020-06-03 12:31:30 +00:00
Aditi Sinha 88bc1f09cb Characterization for extra rows 2020-02-20 17:01:52 +00:00
Matt Guthaus 289d3b3988 Feedthru port edits. 
Comment about write driver size for write through to work, but
disable write through in functional simulation.
Provide warning in Verilog about write throughs.
 2019-09-27 14:18:49 -07:00
Matt Guthaus 9ec663e0b1 Write all write ports first cycle. Don't check feedthru. 2019-09-07 20:20:44 -07:00
Matt Guthaus 35a8dd2eec Factor out masking function 2019-09-07 20:05:05 -07:00
Matt Guthaus e5db02f7d8 Fix wrong function. Except unknown ports. 2019-09-06 14:59:23 -07:00
Matt Guthaus b5b0e35c8a Fix syntax error. 2019-09-06 12:29:28 -07:00
Matt Guthaus 86c22c8904 Clean and simplify simulation code. Feedthru check added. 2019-09-06 12:09:12 -07:00
Matt Guthaus 969cca28e4 Enable sensing during writes. Need to add dedicated test. 2019-09-06 07:16:50 -07:00
Matt Guthaus 678b2cc3fa Fix functional test clk name 2019-09-04 18:59:08 -07:00
Matt Guthaus ee2456f433 Merge branch 'add_wmask' into dev 2019-08-22 15:01:41 -07:00
Matt Guthaus 9f54afbf2c Fix capitalization in verilog golden files 2019-08-21 14:29:57 -07:00
Matt Guthaus d0f04405a6 Convert capital names to lower case for consistency 2019-08-21 13:45:34 -07:00
jsowash a6bb410560 Begin implementing a write mask layout as the port data level. 2019-08-07 09:12:21 -07:00
Matt Guthaus a8d09acd40 Use ordered dict instead of sorting keys 2019-08-01 12:21:30 -07:00
Matt Guthaus d403362183 Sort keys for random read address choice. 2019-08-01 11:32:49 -07:00
Hunter Nichols 24b1fa38a0 Added graph fixes to handmade multiport cells. 2019-07-30 20:31:32 -07:00
Hunter Nichols c12dd987dc Fixed pbitcell graph edge formation. 2019-07-30 00:49:43 -07:00
Matt Guthaus 468a759d1e Fixed control problems (probably) 
Extended functional tests for 15 cycles (slow, but more checking)
Fixed s_en to be gated AFTER the RBL.
 2019-07-27 11:09:08 -07:00
Matt Guthaus 0c5cd2ced9 Merge branch 'dev' into rbl_revamp 2019-07-26 18:01:43 -07:00
Matt Guthaus 3327fa58c0 Add some signal names to functional test comments 2019-07-26 14:49:53 -07:00
jsowash de485182bc Cleaned up comments about wmask. 2019-07-25 13:21:17 -07:00
jsowash 61ba23706c Removed comments for rw pen() and added a wmask func test. 2019-07-25 12:24:27 -07:00