luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
4,419 Commits 4 Branches 63 Tags 78 MiB
Commit Graph

4419 Commits

Author SHA1 Message Date
samuelkcrow 67c1560df0 forgot other place with cs_buf 2022-07-21 19:35:01 -07:00
samuelkcrow fede082b80 cs instead of cs_buf now that everything else is working 2022-07-21 19:35:01 -07:00
samuelkcrow 30b9c2fc25 remove glitch inverters from placement functions, move glitch1 to pen row 2022-07-21 19:35:01 -07:00
samuelkcrow 606260dd68 use odd number inverter chains from delay chain for delay instead of external inverters 2022-07-21 19:35:01 -07:00
samuelkcrow b9b57ab6b3 double length of delay chain as well 2022-07-21 19:35:01 -07:00
samuelkcrow 06254fae72 forgot to multiply all delay chain pinouts by 2 because of previous design that only exposed pins for even numbered inverters in delay chain... oops 2022-07-21 19:35:01 -07:00
samuelkcrow 1d0741baa4 temporariliy commenting out path code that's making simulation fail. 2022-07-21 19:35:01 -07:00
samuelkcrow ef2c9fe296 exclude rbl connection in sram base for delay control logic 2022-07-21 19:35:01 -07:00
samuelkcrow 7d4b718344 add most functions needed for delay control logic, fix multi-delay pin order issue 2022-07-21 19:35:01 -07:00
samuelkcrow 45239ca2a9 use cs_buf for sense amp on r ports instead of cs 2022-07-21 19:35:01 -07:00
samuelkcrow c4138c9f9b typo in cs buf netlist function 2022-07-21 19:35:01 -07:00
samuelkcrow 2b72fbee4e bug fix list vs set 2022-07-21 19:35:01 -07:00
samuelkcrow 11ea82e782 check delay chain pinout list, add cs_buf to control logic 2022-07-21 19:35:01 -07:00
samuelkcrow 78013d32b7 hard-code multi-delay stages 2022-07-21 19:35:01 -07:00
samuelkcrow 62a65f8053 all remaining spice for delay control 2022-07-21 19:35:01 -07:00
samuelkcrow 66502fc5dc new control logic module with no more rbl logic, added glitches so far 2022-07-21 19:35:01 -07:00
samuelkcrow b05a721fb5 spice for delay chain with all inverter outputs as pins 2022-07-21 19:35:01 -07:00
samuelkcrow e1fcd90b59 backing up spice attempts 2022-07-21 19:35:01 -07:00
Bugra Onal 6d6063ef4e modified template engine & sram multibank class 2022-07-21 15:56:29 -07:00
Bugra Onal a497943be3 Template section clone method 2022-07-21 15:45:50 -07:00
Bugra Onal b75e1fc499 Template section clone method 2022-07-21 15:45:50 -07:00
Bugra Onal f2cd611cb8 TEmplate rework 2022-07-21 15:45:50 -07:00
Bugra Onal 988399ba73 Base-verilog 2022-07-21 15:45:50 -07:00
Bugra Onal 06c56c256e Base template additions 2022-07-21 15:45:50 -07:00
Bugra Onal 3d3a8202fe Verilog Template additions 2022-07-21 15:45:50 -07:00
Bugra Onal be9fadf1bb Base verilog template init 2022-07-21 15:45:50 -07:00
Bugra Onal 874d965edb Template module done 2022-07-21 15:45:50 -07:00
Bugra Onal 99b517d55a Bank select 2022-07-21 15:45:50 -07:00
Bugra Onal 54a012b574 Templatable verilog file 2022-07-21 15:45:50 -07:00
mrg 0d616ae072 Merge branch 'dev' into stable 2022-07-21 09:37:24 -07:00
mrg 6707a93c3c Add fudge factor for bitcell array side rail spacings to fix DRC in freepdk45. 2022-07-20 10:27:30 -07:00
mrg 5ad97aa636 Update README and setpaths with new PYTHONPATH 2022-07-20 10:27:10 -07:00
mrg 3b0533c9c7 v1.2.0 2022-07-17 19:55:05 -07:00
mrg c406e2a9da Make macros use same DOCKER_CMD. 2022-07-13 17:19:25 -07:00
mrg ff7ceaf92d Fix syntax error for module scope in row/col caps. 2022-07-13 17:19:09 -07:00
Bugra Onal 6a4bd62206 Added unit test for multibank 2022-07-13 16:40:21 -07:00
Bugra Onal aada5a0d09 Not mathcing whitespace bug fixed 2022-07-13 16:38:22 -07:00
Bugra Onal e041b101a7 Fixed the bad commas with post-process regex 2022-07-13 16:37:47 -07:00
Bugra Onal 94f166e2d0 None check syntax fix 2022-07-13 16:36:14 -07:00
Bugra Onal 45d8c43376 write_size init in sram_config 2022-07-13 16:20:06 -07:00
Bugra Onal a38826f073 Fixed indent error on write_size init 2022-07-13 16:11:45 -07:00
mrg d92c7a634d Use packages for imports. 
Must set PYTHONPATH to include OPENRAM_HOME now.
Reorganizes subdirs as packages.
Rewrites unit tests to use packages.
Update README.md with instructions, dependencies etc.
Update sky130 module imports.
Change tech specific package from modules to custom.
 2022-07-13 15:55:57 -07:00
Bugra Onal 78d4e2aa8b Cleaned up tests dir after bad run 2022-07-08 17:03:53 -07:00
Bugra Onal 4028534a84 Fixed verilog filename double extension 2022-07-08 17:01:30 -07:00
Bugra Onal 289f48c3f3 Merge branch 'multibank' of github.com:VLSIDA/PrivateRAM into multibank 2022-07-08 14:23:05 -07:00
Bugra Onal 3647acda9e Fixed globals conflict 2022-07-08 14:17:51 -07:00
Bugra Onal a1645570a8 Replaced instances of addr_size with bank_addr 2022-07-08 13:55:02 -07:00
Bugra Onal 660226c192 Set write_size default to word_size 2022-07-08 13:54:56 -07:00
Bugra Onal 2c6d3223ea Added conditional sections to template 2022-07-08 13:51:07 -07:00
Bugra Onal 34f28554ad Multibank file generation (messy) 2022-07-08 13:51:07 -07:00