mrg
0c280e062a
Fix func test with row/col of 0. PEP8 cleanup. Smaller global test case.
2020-09-29 11:35:58 -07:00
mrg
4b5bbe755f
PEP8 cleanup. Fix cur_slew bug.
2020-09-29 11:13:58 -07:00
mrg
d7e2340e62
Lots of PEP8 cleanup. Refactor path graph to simulation class.
2020-09-29 10:26:31 -07:00
mrg
4a987bef9a
Merge branch 'wlbuffer' into dev
2020-09-28 15:51:45 -07:00
mrg
88731ccd8e
Fix rounding error for wmask with various word_size
2020-09-28 09:53:01 -07:00
mrg
c7d32089f3
Create RBL wordline buffer with correct polarity.
2020-09-17 14:45:49 -07:00
mrg
71d86f88b0
Merge branch 'dev' into wlbuffer
2020-09-10 13:05:14 -07:00
mrg
8e91ec1770
Add check_pins function
2020-09-08 13:31:50 -07:00
Hunter Nichols
8bcbf005bf
Merge branch 'dev' into characterizer_bug_fixes
2020-09-04 02:25:01 -07:00
Hunter Nichols
13b1d4613c
Moved spice naming checking code from design to the spice base module
2020-08-31 14:36:13 -07:00
mrg
c1c1535210
Merge branch 'wlbuffer' into dev
2020-08-27 15:44:29 -07:00
Hunter Nichols
42f2ff679e
Removed dead code from delay and base module related to characterization
2020-08-27 15:40:41 -07:00
mrg
11a82b7283
Fixed local bitcell array for single and dual port
2020-08-27 14:03:05 -07:00
jcirimel
9cecf367ee
Merge branch 'dev' into pex
2020-08-17 17:49:41 -07:00
jcirimel
714b57d48e
Merge branch 'dev' into pex
2020-08-17 17:48:21 -07:00
mrg
3a692e2846
Comment updates
2020-08-17 14:35:39 -07:00
mrg
30976df48f
Change inheritance inits to use super
2020-08-06 11:33:26 -07:00
jcirimel
df4a231c04
fix merge conflicts
2020-07-21 11:38:34 -07:00
mrg
2ccf3aea3b
Set channel route height and width (of routes, not pins)
2020-07-20 13:25:47 -07:00
mrg
f87b427f76
Add parent to channel route for dumpign debug gds.
2020-07-20 12:03:25 -07:00
mrg
7385decbff
Add channel route cyclic VCG debugging.
2020-07-20 12:02:30 -07:00
mrg
9d5d632d1a
Pins may be below the channel.
2020-07-16 14:23:48 -07:00
mrg
ba3d32fa0c
Starting to implement minimizing channel router (not done)
2020-07-16 13:21:44 -07:00
mrg
e49236f8fc
Default drc and lvs errors is skipped.
2020-07-13 14:08:00 -07:00
mrg
716798baae
Convert all DRC and LVS routines to set member variables for drc_errors and lvs_errors.
2020-07-13 13:01:00 -07:00
mrg
2011974e01
Make drc and lvs errors a member variable. Run only once.
2020-07-13 12:49:24 -07:00
mrg
27166c75f0
Don't remove temp files during regular openram runs.
2020-07-03 07:00:56 -07:00
mrg
c340870ba0
Channel route dout wires as well in read write ports
2020-07-01 14:44:01 -07:00
mrg
3d0f29ff3a
Fix missing via LVS issues. LVS passing for some 20 tests.
2020-07-01 09:22:59 -07:00
mrg
c1fedda575
Modifications for min area metal.
...
Made add_via_stack_center iterative instead of recursive.
Removed add_via_stack (non-center) since it isn't used.
Add min area metal during iterative via insertion.
2020-06-30 15:07:34 -07:00
mrg
8cedeeb3d9
Widen pitch of control bus in bank.
2020-06-30 10:57:41 -07:00
Matt Guthaus
9b939c9a1a
DRC/LVS and errors fixes.
...
Only enact pdb if assert fails in debug.error.
Only run drc/lvs one time in parse_info by saving result.
Cleanup drc/lvs output.
2020-06-30 07:16:05 -07:00
Matt Guthaus
e97644c424
Only do reverse lookup on valid interconnect layers since layer numbers can be shared.
2020-06-29 14:42:24 -07:00
mrg
07d0f3af8e
Only copy end-cap pins to the bank level
2020-06-29 11:46:59 -07:00
mrg
47f541df0e
Fix bugs in channel route.
2020-06-28 16:58:28 -07:00
mrg
709535f90f
Fix right perimeter pin coordinate bug
2020-06-28 14:47:17 -07:00
mrg
bc3de9db05
Pick correct side of pin in channel route.
2020-06-28 14:28:18 -07:00
mrg
94d7000717
Reduce output clutter from gds write
2020-06-26 12:16:54 -07:00
mrg
567675ab31
PEP8 cleanup
2020-06-26 11:47:12 -07:00
mrg
d53abba479
Always route the channel route since it is it's own design.
2020-06-25 17:43:44 -07:00
mrg
f11afaa63d
Refactor channel route to be a design.
2020-06-25 17:30:03 -07:00
mrg
4bc3df8931
Add get_tx_insts and expand add_enclosure
2020-06-24 11:54:36 -07:00
mrg
cddb16dabc
Separate active and poly contact to gate rule
2020-06-24 09:17:39 -07:00
mrg
83001e1ab5
PEP8 formatting
2020-06-23 15:39:26 -07:00
mrg
e849a9b973
Use different LVS libs based on tech and sky130
2020-06-23 14:53:24 -07:00
mrg
031862c749
Add metal enclosure to base case of center via stack.
2020-06-23 11:56:50 -07:00
mrg
54120f8405
Add option for removing subckt/instances of cells for row/col caps
2020-06-22 12:35:37 -07:00
mrg
a13d535945
PEP8 cleanup
2020-06-22 11:33:02 -07:00
mrg
78be9f367a
Add brain-dead router pins to perimeter
2020-06-14 15:52:09 -07:00
mrg
8f1dc7eeea
Include mirror/rotate on translate_all boundary update
2020-06-13 06:50:53 -07:00
mrg
Hunter Nichols
jcirimel