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OpenRAM
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872 Commits

Author SHA1 Message Date
Matt Guthaus 22b5010734 Skip pmulti which has LVS fail 2018-10-10 16:01:55 -07:00
Matt Guthaus 96d3cacb9c Skip func tests that are failing 2018-10-10 16:00:21 -07:00
Matt Guthaus 9bb1c2bbcf Fix Future Warning for real 2018-10-10 15:58:16 -07:00
Matt Guthaus 13e83e0f1a Separate 1bank tests 2018-10-10 15:58:00 -07:00
Matt Guthaus fa4dd8881c Fix Future warnings comparison to None 2018-10-10 15:47:14 -07:00
Matt Guthaus 6bbf66d55b Rewrote pin enclosure code to better address off grid pins. 
Include only maximal pin enclosure shapes.
Add smallest area connector for off grid pins.
Fix decoder to use add_power_pin code.
Change permissions.
 2018-10-10 15:15:58 -07:00
Matt Guthaus a2b1d025ab Merge multiport 2018-10-08 11:45:50 -07:00
Matt Guthaus 3244e01ca1 Add copy power pin function 2018-10-08 09:56:39 -07:00
Matt Guthaus 280488b3ad Add M3 supply to pinvbuf 2018-10-08 09:24:16 -07:00
Michael Timothy Grimes 6ef1a3c755 Improvements to functional test. Now will read or write in a random sequence, using randomly generated words and addresses, and using random ports in the multiported cases. Functional test still has some bugs that are being worked out so it will sometimes fail and sometimes not fail. 2018-10-08 06:34:36 -07:00
Matt Guthaus 06dc910390 Route supply after moving origin 2018-10-06 14:03:00 -07:00
Matt Guthaus 8499983cc2 Add supply router to top-level SRAM. Change get_pins to elegantly fail. 2018-10-06 08:30:38 -07:00
Matt Guthaus 83fd2c0512 Fix openram_temp directory 2018-10-06 08:08:01 -07:00
Matt Guthaus 94ab69ea16 Supply router working, perhaps not efficiently though. 2018-10-05 15:57:34 -07:00
Matt Guthaus eb2304944b Fix .magicrc file name 2018-10-05 08:48:25 -07:00
Matt Guthaus 12cb02a09f Add partial grids as pins. Add previous paths as routing targets. 2018-10-05 08:39:28 -07:00
Matt Guthaus c0ffa9cc7b Clean up magic config file copying. Add warning for missing files. 2018-10-05 08:36:12 -07:00
Matt Guthaus b3fa6b9d52 Make setup.tcl file a technology file 2018-10-05 08:30:25 -07:00
Matt Guthaus 19114fe47f Add commented extraction when running DRC only 2018-10-05 08:18:53 -07:00
Matt Guthaus bb83e5f1be Move clk up in dff arrays for supply pin access 2018-10-05 08:18:38 -07:00
Matt Guthaus 68b30d601e Move bitcells to their own directory in preparation for custom multiport cells. 2018-10-05 08:09:09 -07:00
Hunter Nichols 7b4e001885 Altered web to only be generated for rw ports. 2018-10-04 15:08:12 -07:00
Matt Guthaus c3cd76048b Removed prints. Fixed offset for single track enclosure. 2018-10-04 14:44:25 -07:00
Hunter Nichols 371a57339f Fixed bugs to allow characterization of multiple read ports. Improved some debug messages. 2018-10-04 14:09:09 -07:00
Hunter Nichols 6e0a1b8823 Fixed bugs in power simulations. Made regex raw strings to remove warnings 2018-10-04 14:09:09 -07:00
Hunter Nichols c876bbfe73 Changed characterizer control generation to match recent changes in multiport. 2018-10-04 14:09:09 -07:00
Hunter Nichols 2e322be7f7 Added changes the control logic PWL generation to match changes made in stimuli. 2018-10-04 14:09:09 -07:00
Hunter Nichols 88f2238e03 Multiport variable bug fix and removed unused code. 2018-10-04 14:09:09 -07:00
Hunter Nichols bb79d9a62d Added regex pattern matching to trim_spice to handle multiport. 2018-10-04 14:09:09 -07:00
Hunter Nichols e7f92e67d0 Fixed issues with inst_sram that prevented functional test from running after merge. 2018-10-04 14:09:01 -07:00
Hunter Nichols 6c537c4884 Made stim node names more ngspice friendly for interactive mode. Cleaned up cycle comments. Changed ground names in stim and added related comments. 2018-10-04 14:06:43 -07:00
Hunter Nichols 65edc70cfd Made global names for pins types. Fixed bugs in tests. 2018-10-04 14:06:43 -07:00
Hunter Nichols d2120d6910 Moved pin name creation from stimuli to delay and bug fix in find_feasible_period_one_port 2018-10-04 14:06:34 -07:00
Matt Guthaus 985d04d4b5 Cleanup of router. 
Made offsets in geometry snap to grid.
Changed gds_write to use list for visited flag.
Rewrite self.gds each call in case of any changes.
 2018-10-04 14:04:29 -07:00
Hunter Nichols 4586ed343f Edited lib to support port indexing. Edited tests in reaction to name dict name changes. Cleaned up measurement value generation in delay. 2018-10-04 14:04:08 -07:00
Hunter Nichols ab7d3510b5 Cleaned up result tables to be indexed by port and measurement name. Lib has not been updated, so it crashes there. 2018-10-04 14:04:08 -07:00
Hunter Nichols 346b188372 Improved on some hard coded values which determine the measurements. 2018-10-04 14:04:08 -07:00
Hunter Nichols cfe15d48a4 Added changes to make changing the names of the measurements simple in delay.py. Results in some hardcoded values which is TODO for a fix. 2018-10-04 14:04:08 -07:00
Hunter Nichols aa0d032c78 Cleaned the char_data to fit the previous style. Added print statements to load/slew sims. 2018-10-04 14:04:08 -07:00
Michael Timothy Grimes cf4b216888 Correcting functional inheritance from simulation. 2018-10-04 13:55:59 -07:00
Michael Timothy Grimes e258199fa3 Removing we_b signal from write ports since it is redundant. 2018-10-04 09:31:04 -07:00
Michael Timothy Grimes 34d8a19871 Adding simulation.py for common functions between functional and delay tests. Updating functional test. 2018-10-04 09:29:44 -07:00
Michael Timothy Grimes bea6b0b5dc Renaming functional tests to include spice exe used. Renaming pex test to separate functional tests from pex test. 2018-09-30 22:39:37 -07:00
Michael Timothy Grimes 6d83ebf50f updating debug messages in functional test 2018-09-30 22:10:11 -07:00
Michael Timothy Grimes 8a56dd2ac9 Finished functional test 2018-09-30 21:20:01 -07:00
Michael Timothy Grimes 26c6232564 Updating functional test. Test can now run a spice simulation and read the dout values from the timing files. 2018-09-28 23:38:48 -07:00
Michael Timothy Grimes a71486e22f Adding mutliport constants to design.py to reduce the need for copied code across multiple modules. 2018-09-28 00:11:39 -07:00
Michael Timothy Grimes 66933ed922 Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-09-27 02:02:24 -07:00
Michael Timothy Grimes 19d68f613e Making changes to bank select for multiport. The height of the nor gate using pbitcell was too short and one of the contacts violated drc. Extended height of nor by drc spacing violation so it could pass in multiport. 2018-09-27 02:01:32 -07:00
Michael Timothy Grimes 1ca0154027 Editting top level netlist for multiport. Now there are multiple control logic modules, one per port. Since diffent ports are driven by different clocks, also separating dff modules, one per port. 2018-09-26 19:10:24 -07:00