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OpenRAM
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3,408 Commits 4 Branches 63 Tags 78 MiB
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100 Commits

Author SHA1 Message Date
mrg 19ea33d43d Move delay line module down. 2021-05-04 16:42:42 -07:00
mrg 4a40e96f6d Control logic route changes. 
Move wl_en to top control signal.
Route wl_en directly to port_address.
Reorder input bus to bank.
 2021-03-24 14:32:10 -07:00
mrg 9f0ab0d081 Route perimeter signals before power grid 2021-02-26 11:14:39 -08:00
Matt Guthaus 30fc81a1f0 Update copyright year. 2021-01-22 11:23:28 -08:00
mrg 69fe050bad Refactor and cleanup router grids. 2021-01-15 13:25:57 -08:00
mrg 6f5b7c0264 Flatten bug fixed in Magic so don't flatten routes. 2021-01-12 16:20:03 -08:00
mrg ec6f0f1873 Escape route to any side 2021-01-06 09:40:32 -08:00
mrg c89e156bfe Separate add pins and route pins so pins can block supply router. 2020-12-23 10:49:47 -08:00
mrg 94b1e729ab Don't add vias when placing dff array 2020-12-22 17:08:53 -08:00
mrg 286ac635d6 Escape router changes. 
Rename exit router to escape router.
Perform supply and signal escape routing after channel and other routing.
 2020-12-22 16:35:05 -08:00
mrg 52119fe3b3 Cleanup exit route. Pins are on perimeter mostly. 2020-12-22 15:56:51 -08:00
mrg ae1c889235 Updates to IO signal router. 
Route signals to perimeter using maze router.
Move IO pins without perimeter pins to M3 using add_io_pin (like add_power_pin).
 2020-12-22 09:39:58 -08:00
mrg 348001b1c8 Supply tree uses signal grid. PEP8 cleanup. 2020-12-21 13:51:50 -08:00
mrg c0ab0af201 Retry routes with expanding detour allowed. 2020-12-17 11:39:17 -08:00
mrg f55b57033d Route col decoder address with data bits in channel 2020-12-15 16:37:23 -08:00
mrg 878a9cee8a Add channel routes as flat instances to appease Magic extraction. 2020-12-15 16:01:39 -08:00
mrg da721a677d Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
mrg 18c8ad265e Unique name for sram channel routes 2020-10-01 09:55:34 -07:00
mrg 449a4c2660 Exclude bitcells in other local areas not of interest 2020-09-29 12:15:42 -07:00
Hunter Nichols 73b2277daa Removed dead code related to older characterization scheme 2020-08-27 17:30:58 -07:00
mrg 652f160aca Merge branch 'wlbuffer' into dev 2020-08-25 15:50:08 -07:00
mrg bd8bf9afd8 Remove RBL label at top level of SRAM 2020-08-25 14:42:21 -07:00
mrg 28bd93bf51 Still working on array refactor 2020-08-25 11:50:44 -07:00
jcirimel 9cecf367ee Merge branch 'dev' into pex 2020-08-17 17:49:41 -07:00
jcirimel 714b57d48e Merge branch 'dev' into pex 2020-08-17 17:48:21 -07:00
mrg f23d2e36a7 Don't obstruct control logic signals with dffs when no column mux. 2020-07-29 10:31:18 -07:00
jcirimel df4a231c04 fix merge conflicts 2020-07-21 11:38:34 -07:00
mrg 58846a4a25 Limit wordline driver size. Place row addr dff near predecoders. 2020-07-20 17:57:38 -07:00
mrg 0ed81aa923 Removed extraneous shift from added mirroring 2020-07-20 14:11:52 -07:00
mrg 82bbacdfb5 Add data bus gap to dynamically computed channel width 2020-07-20 13:43:57 -07:00
mrg a36e89e103 Replace data flops depending on channel width 2020-07-20 13:26:05 -07:00
mrg f35848e4f8 Route col flops separately. Flip port 1 col flop for easier routing. 2020-07-20 12:02:59 -07:00
mrg ba3d32fa0c Starting to implement minimizing channel router (not done) 2020-07-16 13:21:44 -07:00
mrg d48f483248 Fix swapped instance bug in perimeter pins. 2020-07-01 15:10:20 -07:00
mrg c340870ba0 Channel route dout wires as well in read write ports 2020-07-01 14:44:01 -07:00
mrg 3d0f29ff3a Fix missing via LVS issues. LVS passing for some 20 tests. 2020-07-01 09:22:59 -07:00
mrg 5626fd182e Extra track in data bus. Remove old code. 2020-06-30 10:58:24 -07:00
mrg 5f3a45b91b Compute bus size separately for ports 2020-06-29 05:54:30 -07:00
mrg 751eab202b Move row addr flops away from predecode. Route spare wen separately on lower layer. 2020-06-28 15:06:29 -07:00
mrg 4df02dad67 Move spare wen_dff to the right by spare columns 2020-06-28 14:28:43 -07:00
mrg 0c9f52e22f Realign col decoder and control by 1/4 so metal can pass over 2020-06-28 07:15:06 -07:00
mrg 66ea559209 Use channel for dffs all at once 2020-06-27 08:23:12 -07:00
mrg 7220b23402 Add riscv unit tests 2020-06-25 15:34:18 -07:00
mrg 52ee7b0a19 Disable perimeter pins and make an option 2020-06-14 16:44:10 -07:00
mrg 78be9f367a Add brain-dead router pins to perimeter 2020-06-14 15:52:09 -07:00
Aditi Sinha d5041afebc Merge branch 'dev' into bisr 2020-06-07 16:27:25 +00:00
mrg 717188f85c Change L shape of rbl route 2020-06-04 11:03:39 -07:00
Aditi Sinha eb0c595dbe SRAM layout and functional tests with spare cols 2020-06-03 12:31:30 +00:00
Aditi Sinha c7d86b21ae Spare cols with wmask enabled 2020-05-16 10:09:03 +00:00
Aditi Sinha 8bd1052fc2 Spare columns in full sram layout 2020-05-14 10:30:29 +00:00