17 Commits

Include renames

Author	SHA1	Message	Date
Eren Dogan	0a1de57cae	Update copyright year	2024-01-03 14:32:44 -08:00
Sam Crow	006eacd6d0	add pinout message output	2023-06-25 10:46:58 -07:00
Sam Crow	a51b71d460	update copyright	2023-06-08 12:36:12 -07:00
samuelkcrow	a48842ff72	fix code format issues from 00 test	2023-06-07 15:52:25 -07:00
Sam Crow	157935c915	update test/module imports related to delay control	2023-06-06 13:12:20 -07:00
samuelkcrow	b82213caff	use packages for imports in modules	2022-07-22 12:56:47 -07:00
samuelkcrow	5fa0689c02	fix drc error in wlen_row	2022-07-21 19:35:02 -07:00
samuelkcrow	08ac1c176a	connect in pin via m2 instead of m3, passes lvs now	2022-07-21 19:35:02 -07:00
samuelkcrow	12c58b0457	use spice names for delay chain output pins in layout	2022-07-21 19:35:02 -07:00
samuelkcrow	74bf3770d9	move pins to m3, route in pin down to avoid m3 collision	2022-07-21 19:35:02 -07:00
samuelkcrow	1e1ec54275	fix indentation errors, typos, and missing iterator	2022-07-21 19:35:02 -07:00
samuelkcrow	1d6bd78612	multi-delay layout pins and routing for them in control logic	2022-07-21 19:35:01 -07:00
samuelkcrow	7d4b718344	add most functions needed for delay control logic, fix multi-delay pin order issue	2022-07-21 19:35:01 -07:00
samuelkcrow	2b72fbee4e	bug fix list vs set	2022-07-21 19:35:01 -07:00
samuelkcrow	11ea82e782	check delay chain pinout list, add cs_buf to control logic	2022-07-21 19:35:01 -07:00
samuelkcrow	62a65f8053	all remaining spice for delay control	2022-07-21 19:35:01 -07:00
samuelkcrow	66502fc5dc	new control logic module with no more rbl logic, added glitches so far	2022-07-21 19:35:01 -07:00