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2624 Commits

Author SHA1 Message Date
Akash Levy 099a3c881b
Merge pull request #150 from Silimate/reenable_vhdl 
Reenable VHDL
 2026-04-22 04:10:29 -07:00
Akash Levy bf40364bd0 No operator optimization, but it passes all tests 2026-04-22 03:12:26 -07:00
Akash Levy 8485d57841 opt_expr for constant comparisons 2026-04-20 02:03:35 -07:00
Akash Levy 083eb8e5f1 Try again 2026-04-16 04:16:55 -07:00
Akash Levy 0db45a6796 Reenable VHDL 2026-04-16 04:03:31 -07:00
AdvaySingh1 54bcc49987 ENG-1872 2026-04-10 12:54:43 -07:00
Akash Levy 300c64773b Fix offset in splitcells 2026-04-09 16:20:26 -07:00
Akash Levy bf3afc569a Fix the test 2026-04-07 22:46:33 -07:00
Akash Levy 6daa8a01ed opt_vps improvements for VPS read 2026-04-07 22:07:14 -07:00
Akash Levy 1820526a9a opt_vps 2026-04-03 01:15:17 -07:00
Akash Levy 5082625d71 opt_shift 2026-04-02 00:43:06 -07:00
Abhinav Tondapu df43a3097a [ENG-1692] negopt runtime fix + small cleanup 2026-03-30 16:30:46 -07:00
AdvaySingh1 f84fd46a17 Added test cases for clkmerge and cone_partition passes 2026-03-25 15:06:58 -07:00
AdvaySingh1 2836cc8f25 Added test cases for the infer_ce pass 2026-03-04 12:03:38 -08:00
tondapusili f46b8d2a44 silimate: add opt_timing_balance pass and tests 2026-02-27 09:13:39 -08:00
Akash Levy 3e9a5c68b1 Switch back to main Verific without VHDL support 2026-02-18 21:57:14 -08:00
Akash Levy 650c636d39 Fixups 2026-02-18 01:12:35 -08:00
Akash Levy 33c2c88fa4 Bump Yosys to latest from upstream 2026-02-17 23:41:39 -08:00
Miodrag Milanović ac96f318ef
Merge pull request #5676 from YosysHQ/emil/unit-test-by-default 
Run unit tests on make test
 2026-02-13 15:02:50 +01:00
Akash Levy 2b247d165b Merge from main 2026-02-13 04:14:08 -08:00
Miodrag Milanović e4b32d6aae
Merge pull request #5670 from max-kudinov/gowin_mult 
Gowin: Add DSP inference for GW1N and GW2A
 2026-02-12 14:30:27 +01:00
Miodrag Milanovic cc79c6a761 Support building out of tree, but keep always in tests/unit 2026-02-12 12:17:07 +01:00
Maxim Kudinov b055ea05fd gowin: dsp: Add mult inference tests 2026-02-12 14:12:32 +03:00
Gus Smith 7a0774c3bb Don't dump params by default 2026-02-11 08:33:39 -08:00
Gus Smith b0021e5b10 Add tests 2026-02-11 08:10:57 -08:00
Gus Smith e3db8fee6f
Merge pull request #3459 from gs-jgj/feature_dsp48e1_presub 
Add support for subtract in preadder
 2026-02-11 08:02:18 -08:00
Gus Smith 8ab105ac28
Merge pull request #4303 from Coloquinte/sat_choice 
Infrastructure to run a Sat solver as a command
 2026-02-11 06:54:53 -08:00
Gus Smith b04948a8cd Simplify test 2026-02-09 09:38:45 -08:00
tondapusili 6bb43f109c fixed edge cases in negopt passes, fixed cell naming inconsistencies 2026-02-06 16:38:55 -08:00
Robert O'Callahan 34f8582725
Sanitize ABC global and per-run temporary directory names in logs 2026-02-07 12:12:13 +13:00
tondapusili d592f312ab mux_push implementation 2026-02-05 16:49:59 -08:00
Akash Levy 5f7658ca7c
Merge branch 'YosysHQ:main' into main 2026-02-05 13:10:34 -08:00
Emil J 1717fa0180
Merge pull request #5663 from YosysHQ/emil/opt_expr-fix-pow-shift 
opt_expr: fix const lhs of $pow to $shl
 2026-02-05 13:09:01 +01:00
Akash Levy 715e062bcd Merge branch 'main' into negopt-pass-pr 2026-02-04 00:15:53 -08:00
tondapusili 643427d9c9 Add negopt pass with comprehensive pattern matching 
This commit introduces the negopt pass with pre/post optimization modes
for handling negation patterns in arithmetic circuits.

Pre-optimization patterns (expose for tree balancing):
- manual2sub: (a + ~b) + 1 → a - b
- sub2neg: a - b → a + (-b)
- negexpand: -(a + b) → (-a) + (-b) [with output width fix]
- negneg: -(-a) → a
- negmux: -(s ? a : b) → s ? (-a) : (-b)

Post-optimization patterns (cleanup/rebuild):
- negrebuild: (-a) + (-b) → -(a + b)
- muxneg: s ? (-a) : (-b) → -(s ? a : b)
- neg2sub: a + (-b) → a - b

All patterns use nusers() for fanout checking (standard Yosys style).
Comprehensive test coverage with positive/negative cases and formal
verification via equiv_opt.
 2026-02-03 17:21:21 -08:00
Gus Smith 3f01d7a33a Add test 2026-02-03 14:41:08 -08:00
Akash Levy 8e5d24aa6b Bump yosys to latest 2026-02-03 06:08:36 -08:00
Emil J. Tywoniak 3bfeaee8ca opt_expr: fix const lhs of $pow to $shl 2026-02-03 11:59:00 +01:00
Emil J 59653da599
Merge pull request #5609 from nataliakokoromyti/upstream-design-run-pass 
Add Design::run_pass()
 2026-02-02 19:30:18 +01:00
Akash Levy a9cf998f9f Merge from upstream 2026-01-29 17:46:44 -08:00
Natalia 61b1c3c75a use run_pass in ecp5 add/sub test 2026-01-29 02:42:23 -08:00
Natalia 7439d2489e add assertion to run_pass test 2026-01-29 02:23:07 -08:00
Miodrag Milanović 43db5c9488
Merge pull request #5645 from nataliakokoromyti/upstream-verific-mixed-sv-vhdl 
Upstream verific mixed sv vhdl
 2026-01-29 10:12:09 +01:00
Natalia b6c148f84a tests/verific: ensure mixed -f requires VHDL unit 2026-01-28 22:46:10 -08:00
Akash Levy 5993d2fec8 Remove annoying test case 2026-01-28 19:18:06 -08:00
Akash Levy 16087ae931 Merge from upstream 2026-01-28 18:17:50 -08:00
nella 8f6c4d40e4
Merge pull request #5623 from YosysHQ/nella/opt-dff-rewrite 
opt_dff restructure.
 2026-01-28 14:41:40 +01:00
Natalia 5a64fe2d91 tests/verific: assert module count explicitly 2026-01-28 04:21:13 -08:00
Natalia 8c2ef89732 tests/verific: import mixed -f list with -all 2026-01-28 04:13:04 -08:00
Natalia 74c601db0f tests/verific: add mixed -f list case 2026-01-28 03:55:42 -08:00