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Merge pull request #5623 from YosysHQ/nella/opt-dff-rewrite
opt_dff restructure.
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nella
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#ifndef OPT_DFF_COMP_H
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#define OPT_DFF_COMP_H
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#include "kernel/rtlil.h"
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#include <map>
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#include <optional>
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YOSYS_NAMESPACE_BEGIN
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/**
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* Pattern matching utilities for control signal analysis.
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*
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* A pattern_t maps control signals to required values, representing a
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* product term (conjunction): {A=1, B=0} means "A AND !B".
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*
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* A patterns_t is a set of patterns representing a sum-of-products:
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* {{A=1, B=0}, {A=0, C=1}} means "(A AND !B) OR (!A AND C)".
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*
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* Used for analyzing MUX tree control paths in DFF optimization.
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*/
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// Pattern matching for clock enable
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// A pattern maps control signals to their required values for a MUX path
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typedef std::map<RTLIL::SigBit, bool> pattern_t; // Set of control signals that must ALL match required vals
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typedef std::set<pattern_t> patterns_t; // Alternative patterns (OR)
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typedef std::pair<RTLIL::SigBit, bool> ctrl_t; // Control signal
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typedef std::set<ctrl_t> ctrls_t; // Set of control signals that must ALL be active
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/**
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* Find if two patterns differ in exactly one variable.
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* Example: {A=1,B=1} vs {A=1,B=0} returns B, allows simplification: (A&B) | (A&!B) => A
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*/
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inline std::optional<RTLIL::SigBit> find_complementary_pattern_var(
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const pattern_t& left,
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const pattern_t& right
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) {
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std::optional<RTLIL::SigBit> ret;
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for (const auto &pt : left) {
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// Left requires signal that right doesn't constrain - incompatible domains
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if (right.count(pt.first) == 0)
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return std::nullopt;
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// Signal has same required value in both - not the complement variable
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if (right.at(pt.first) == pt.second)
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continue;
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// Already found one differing signal, now found another - not simplifiable
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if (ret)
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return std::nullopt;
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// First differing signal - candidate complement variable
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ret = pt.first;
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}
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return ret;
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}
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/**
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* Simplify a sum-of-products by merging complementary patterns: (A&B) | (A&!B) => A,
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* and removing redundant patterns: A | (A&B) => A
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*/
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inline void simplify_patterns(patterns_t& patterns) {
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auto new_patterns = patterns;
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// Merge complementary patterns
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bool optimized;
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do {
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optimized = false;
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for (auto i = patterns.begin(); i != patterns.end(); i++) {
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for (auto j = std::next(i, 1); j != patterns.end(); j++) {
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const auto& left = (GetSize(*j) <= GetSize(*i)) ? *j : *i;
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auto right = (GetSize(*i) < GetSize(*j)) ? *j : *i;
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const auto complementary_var = find_complementary_pattern_var(left, right);
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if (complementary_var && new_patterns.count(right)) {
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new_patterns.erase(right);
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right.erase(complementary_var.value());
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new_patterns.insert(right);
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optimized = true;
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}
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}
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}
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patterns = new_patterns;
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} while(optimized);
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// Remove redundant patterns
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for (auto i = patterns.begin(); i != patterns.end(); ++i) {
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for (auto j = std::next(i, 1); j != patterns.end(); ++j) {
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const auto& left = (GetSize(*j) <= GetSize(*i)) ? *j : *i;
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const auto& right = (GetSize(*i) < GetSize(*j)) ? *j : *i;
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bool redundant = true;
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for (const auto& pt : left)
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if (right.count(pt.first) == 0 || right.at(pt.first) != pt.second)
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redundant = false;
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if (redundant)
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new_patterns.erase(right);
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}
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}
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patterns = std::move(new_patterns);
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}
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YOSYS_NAMESPACE_END
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#endif
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,179 @@
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#include <gtest/gtest.h>
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#include "kernel/pattern.h"
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YOSYS_NAMESPACE_BEGIN
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class FindComplementaryPatternVarTest : public ::testing::Test {
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protected:
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RTLIL::Design *design;
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RTLIL::Module *module;
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RTLIL::Wire *wire_a;
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RTLIL::Wire *wire_b;
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RTLIL::Wire *wire_c;
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RTLIL::Wire *bus;
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void SetUp() override {
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design = new RTLIL::Design;
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module = design->addModule(ID(test_module));
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wire_a = module->addWire(ID(a));
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wire_b = module->addWire(ID(b));
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wire_c = module->addWire(ID(c));
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bus = module->addWire(ID(bus), 4);
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}
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void TearDown() override {
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delete design;
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}
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RTLIL::SigBit bit(RTLIL::Wire *w, int offset = 0) {
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return RTLIL::SigBit(w, offset);
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}
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};
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TEST_F(FindComplementaryPatternVarTest, EmptyPatterns) {
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pattern_t left, right;
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auto result = find_complementary_pattern_var(left, right);
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EXPECT_FALSE(result.has_value());
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}
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TEST_F(FindComplementaryPatternVarTest, IdenticalSingleVar) {
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pattern_t left, right;
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left[bit(wire_a)] = true;
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right[bit(wire_a)] = true;
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auto result = find_complementary_pattern_var(left, right);
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EXPECT_FALSE(result.has_value());
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}
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TEST_F(FindComplementaryPatternVarTest, ComplementarySingleVar) {
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pattern_t left, right;
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left[bit(wire_a)] = true;
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right[bit(wire_a)] = false;
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auto result = find_complementary_pattern_var(left, right);
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ASSERT_TRUE(result.has_value());
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EXPECT_EQ(result.value(), bit(wire_a));
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}
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TEST_F(FindComplementaryPatternVarTest, MissingKeyInRight) {
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pattern_t left, right;
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left[bit(wire_a)] = true;
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left[bit(wire_b)] = false;
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right[bit(wire_a)] = true;
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auto result = find_complementary_pattern_var(left, right);
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EXPECT_FALSE(result.has_value());
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}
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TEST_F(FindComplementaryPatternVarTest, TwoVarsOneComplementary) {
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pattern_t left, right;
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left[bit(wire_a)] = true;
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left[bit(wire_b)] = false;
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right[bit(wire_a)] = true;
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right[bit(wire_b)] = true;
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auto result = find_complementary_pattern_var(left, right);
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ASSERT_TRUE(result.has_value());
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EXPECT_EQ(result.value(), bit(wire_b));
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}
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TEST_F(FindComplementaryPatternVarTest, TwoVarsBothComplementary) {
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pattern_t left, right;
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left[bit(wire_a)] = true;
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left[bit(wire_b)] = false;
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right[bit(wire_a)] = false;
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right[bit(wire_b)] = true;
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auto result = find_complementary_pattern_var(left, right);
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EXPECT_FALSE(result.has_value());
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}
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TEST_F(FindComplementaryPatternVarTest, LeftSubsetOfRight) {
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pattern_t left, right;
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left[bit(wire_a)] = true;
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left[bit(wire_b)] = false;
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right[bit(wire_a)] = true;
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right[bit(wire_b)] = true;
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right[bit(wire_c)] = false;
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auto result = find_complementary_pattern_var(left, right);
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ASSERT_TRUE(result.has_value());
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EXPECT_EQ(result.value(), bit(wire_b));
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}
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TEST_F(FindComplementaryPatternVarTest, ThreeVarsAllSame) {
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pattern_t left, right;
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left[bit(wire_a)] = true;
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left[bit(wire_b)] = false;
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left[bit(wire_c)] = true;
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right[bit(wire_a)] = true;
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right[bit(wire_b)] = false;
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right[bit(wire_c)] = true;
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auto result = find_complementary_pattern_var(left, right);
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EXPECT_FALSE(result.has_value());
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}
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TEST_F(FindComplementaryPatternVarTest, PracticalPatternSimplification) {
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pattern_t pattern1, pattern2;
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pattern1[bit(bus, 0)] = true;
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pattern1[bit(bus, 1)] = true;
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pattern2[bit(bus, 0)] = true;
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pattern2[bit(bus, 1)] = false;
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auto result = find_complementary_pattern_var(pattern1, pattern2);
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ASSERT_TRUE(result.has_value());
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EXPECT_EQ(result.value(), bit(bus, 1));
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// Swapped args
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auto result2 = find_complementary_pattern_var(pattern2, pattern1);
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ASSERT_TRUE(result2.has_value());
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EXPECT_EQ(result2.value(), bit(bus, 1));
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}
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TEST_F(FindComplementaryPatternVarTest, MuxTreeClockEnableDetection) {
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pattern_t feedback_path1, feedback_path2;
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feedback_path1[bit(wire_a)] = true;
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feedback_path1[bit(wire_b)] = true;
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feedback_path2[bit(wire_a)] = true;
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feedback_path2[bit(wire_b)] = false;
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auto comp = find_complementary_pattern_var(feedback_path1, feedback_path2);
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ASSERT_TRUE(comp.has_value());
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EXPECT_EQ(comp.value(), bit(wire_b));
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pattern_t simplified = feedback_path1;
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simplified.erase(comp.value());
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EXPECT_EQ(simplified.size(), 1);
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EXPECT_TRUE(simplified.count(bit(wire_a)));
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EXPECT_TRUE(simplified[bit(wire_a)]);
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}
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TEST_F(FindComplementaryPatternVarTest, AsymmetricPatterns) {
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pattern_t left, right;
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left[bit(wire_a)] = true;
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right[bit(wire_a)] = false;
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right[bit(wire_b)] = true;
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right[bit(wire_c)] = false;
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auto result = find_complementary_pattern_var(left, right);
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ASSERT_TRUE(result.has_value());
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EXPECT_EQ(result.value(), bit(wire_a));
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}
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TEST_F(FindComplementaryPatternVarTest, WireOffsetDistinction) {
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pattern_t left, right;
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left[bit(bus, 0)] = true;
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left[bit(bus, 1)] = false;
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right[bit(bus, 0)] = true;
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right[bit(bus, 1)] = true;
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right[bit(bus, 2)] = false;
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auto result = find_complementary_pattern_var(left, right);
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ASSERT_TRUE(result.has_value());
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EXPECT_EQ(result.value(), bit(bus, 1));
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}
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YOSYS_NAMESPACE_END
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