mirror of https://github.com/YosysHQ/yosys.git
opt_vps improvements for VPS read
This commit is contained in:
parent
7575387cc9
commit
6daa8a01ed
File diff suppressed because it is too large
Load Diff
|
|
@ -157,3 +157,85 @@ select -assert-count 1 t:$dff
|
|||
design -reset
|
||||
log -pop
|
||||
|
||||
# =============================================================================
|
||||
# Test 7: SAT equivalence — VPS read vs right-shift reference
|
||||
# Proves opt_vps produces a logically equivalent circuit to a hand-written
|
||||
# right-shift for a 256-bit register with 32-bit read window.
|
||||
# =============================================================================
|
||||
log -header "SAT equivalence: VPS read vs right-shift ref"
|
||||
log -push
|
||||
design -reset
|
||||
verific -cfg veri_optimize_wide_selector 1
|
||||
verific -cfg db_infer_wide_muxes_post_elaboration 0
|
||||
|
||||
read -sv opt_vps_read.sv
|
||||
verific -import opt_vps_read
|
||||
proc; opt_clean
|
||||
opt_vps; opt_clean
|
||||
rename opt_vps_read gate
|
||||
|
||||
read -sv opt_vps_read_ref.sv
|
||||
verific -import opt_vps_read
|
||||
proc; opt_clean
|
||||
rename opt_vps_read gold
|
||||
|
||||
miter -equiv -flatten -make_assert gold gate miter
|
||||
hierarchy -top miter
|
||||
proc; opt; memory; opt
|
||||
clk2fflogic
|
||||
sat -set-init-zero -tempinduct -prove-asserts -verify
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
# =============================================================================
|
||||
# Test 8: SAT self-equivalence — VPS read before vs after opt_vps
|
||||
# Proves opt_vps does not change the functional behavior for VPS reads.
|
||||
# =============================================================================
|
||||
log -header "SAT self-equivalence: VPS read before vs after opt_vps"
|
||||
log -push
|
||||
design -reset
|
||||
verific -cfg veri_optimize_wide_selector 1
|
||||
verific -cfg db_infer_wide_muxes_post_elaboration 0
|
||||
|
||||
read -sv opt_vps_read.sv
|
||||
verific -import opt_vps_read
|
||||
proc; opt_clean
|
||||
rename opt_vps_read gold
|
||||
|
||||
read -sv opt_vps_read.sv
|
||||
verific -import opt_vps_read
|
||||
proc; opt_clean
|
||||
opt_vps; opt_clean
|
||||
rename opt_vps_read gate
|
||||
|
||||
miter -equiv -flatten -make_assert gold gate miter
|
||||
hierarchy -top miter
|
||||
proc; opt; memory; opt
|
||||
clk2fflogic
|
||||
sat -set-init-zero -tempinduct -prove-asserts -verify
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
# =============================================================================
|
||||
# Test 9: Cell count verification — VPS read
|
||||
# After opt_vps, the $pmux should be replaced with a $shr.
|
||||
# =============================================================================
|
||||
log -header "Cell counts: VPS read post-opt_vps"
|
||||
log -push
|
||||
design -reset
|
||||
verific -cfg veri_optimize_wide_selector 1
|
||||
verific -cfg db_infer_wide_muxes_post_elaboration 0
|
||||
|
||||
read -sv opt_vps_read.sv
|
||||
verific -import opt_vps_read
|
||||
proc; opt_clean
|
||||
opt_vps; opt_clean
|
||||
|
||||
select -assert-none t:$pmux
|
||||
select -assert-count 1 t:$shr
|
||||
select -assert-count 1 t:$dff
|
||||
select -assert-count 1 t:$mux
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,17 @@
|
|||
// Minimal variable-part-select (VPS) read: extracts a 32-bit word
|
||||
// from a 256-bit register at a dynamic byte offset.
|
||||
module opt_vps_read (
|
||||
input logic clk,
|
||||
input logic wr_en,
|
||||
input logic [7:0] index,
|
||||
input logic [255:0] wdata,
|
||||
output logic [31:0] q
|
||||
);
|
||||
logic [255:0] reg_data;
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (wr_en)
|
||||
reg_data <= wdata;
|
||||
|
||||
assign q = reg_data[index +: 32];
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
// Reference for VPS read: uses right-shift instead of variable part-select.
|
||||
module opt_vps_read (
|
||||
input logic clk,
|
||||
input logic wr_en,
|
||||
input logic [7:0] index,
|
||||
input logic [255:0] wdata,
|
||||
output logic [31:0] q
|
||||
);
|
||||
logic [255:0] reg_data;
|
||||
|
||||
always_ff @(posedge clk)
|
||||
if (wr_en)
|
||||
reg_data <= wdata;
|
||||
|
||||
assign q = (reg_data >> index);
|
||||
endmodule
|
||||
Loading…
Reference in New Issue