mirror of https://github.com/YosysHQ/yosys.git
opt_shift
This commit is contained in:
Akash Levy
parent
72db8885aa
commit
5082625d71
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@ -28,6 +28,17 @@ PEEPOPT_PATTERN = passes/silimate/peepopt_expand.pmg
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passes/silimate/peepopt_expand.h: passes/pmgen/pmgen.py $(PEEPOPT_PATTERN)
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$(P) mkdir -p $(dir $@) && $(PYTHON_EXECUTABLE) $< -o $@ -p peepopt $(filter-out $<,$^)
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OBJS += passes/silimate/opt_shift.o
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GENFILES += passes/silimate/peepopt_shift.h
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passes/silimate/opt_shift.o: passes/silimate/peepopt_shift.h
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$(eval $(call add_extra_objs,passes/silimate/peepopt_shift.h))
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PEEPOPT_PATTERN = passes/silimate/peepopt_combine_shifts.pmg
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PEEPOPT_PATTERN += passes/silimate/peepopt_expand_shifts.pmg
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passes/silimate/peepopt_shift.h: passes/pmgen/pmgen.py $(PEEPOPT_PATTERN)
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$(P) mkdir -p $(dir $@) && $(PYTHON_EXECUTABLE) $< -o $@ -p peepopt $(filter-out $<,$^)
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OBJS += passes/silimate/muxmode.o
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GENFILES += passes/silimate/peepopt_muxmode.h
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passes/silimate/muxmode.o: passes/silimate/peepopt_muxmode.h
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@ -0,0 +1,109 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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* Akash Levy <akash@silimate.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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bool did_something;
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#include "passes/silimate/peepopt_shift.h"
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struct OptShiftPass : public Pass {
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OptShiftPass() : Pass("opt_shift", "shift optimizations: combine and expand") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" opt_shift [options] [selection]\n");
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log("\n");
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log("This pass performs shift optimizations.\n");
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log("\n");
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log(" -combine\n");
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log(" Combine nested shift operations (works with all\n");
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log(" combinations of $shl/$sshl and $shr/$sshr):\n");
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log(" (a <</<< b) <</<< c ===> a <</<< (b + c)\n");
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log(" (a >>>/>> b) >>>/>> c ===> a >>>/>> (b + c)\n");
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log(" (a <</<< b) >>>/>> c ===> a <</<< (b - c)\n");
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log(" (a >>>/>> b) <</<< c ===> a >>>/>> (b - c)\n");
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log(" Result uses the inner shift's type.\n");
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log("\n");
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log(" -expand\n");
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log(" Expand shifts across binary operations:\n");
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log(" (a OP b) << c ===> (a << c) OP (b << c)\n");
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log(" (a OP b) >> c ===> (a >> c) OP (b >> c)\n");
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log(" where OP in {$and, $or, $xor, $add, $sub}\n");
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log("\n");
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log(" -max_iters n\n");
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log(" max number of pass iterations to run.\n");
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log("\n");
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log("If neither -combine nor -expand is given, both are run.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing OPT_SHIFT pass (shift optimizations).\n");
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bool run_combine = false;
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bool run_expand = false;
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int max_iters = 10000;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-combine") {
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run_combine = true;
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continue;
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}
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if (args[argidx] == "-expand") {
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run_expand = true;
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continue;
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}
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if (args[argidx] == "-max_iters" && argidx + 1 < args.size()) {
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max_iters = std::stoi(args[++argidx]);
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (!run_combine && !run_expand) {
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run_combine = true;
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run_expand = true;
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}
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for (auto module : design->selected_modules())
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{
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did_something = true;
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for (int i = 0; did_something && i < max_iters; i++)
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{
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did_something = false;
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peepopt_pm pm(module);
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pm.setup(module->selected_cells());
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if (run_combine)
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pm.run_combine_shifts();
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if (run_expand)
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pm.run_expand_shifts();
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}
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}
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}
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} OptShiftPass;
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PRIVATE_NAMESPACE_END
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@ -0,0 +1,91 @@
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pattern combine_shifts
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//
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// Authored by Akash Levy of Silimate, Inc. under ISC license.
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//
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// Combine nested shift operations
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//
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// Same direction:
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// (a << b) << c ===> a << (b + c)
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// (a >> b) >> c ===> a >> (b + c)
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// (a <<< b) <<< c ===> a <<< (b + c)
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// (a >>> b) >>> c ===> a >>> (b + c)
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// (a << b) <<< c ===> a << (b + c)
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// (a <<< b) << c ===> a <<< (b + c)
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// (a >> b) >>> c ===> a >> (b + c)
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// (a >>> b) >> c ===> a >>> (b + c)
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//
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// Mixed direction:
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// (a <</<< b) >>>/>> c ===> a <</<< (b - c)
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// (a >>>/>> b) <</<< c ===> a >>>/>> (b - c)
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//
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state <SigSpec> inner_a inner_b inner_y outer_b outer_y
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match inner_shift
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select inner_shift->type.in($shl, $shr, $sshl, $sshr)
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set inner_a port(inner_shift, \A)
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set inner_b port(inner_shift, \B)
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set inner_y port(inner_shift, \Y)
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endmatch
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code
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if (nusers(inner_y) != 2)
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reject;
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endcode
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match outer_shift
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select outer_shift->type.in($shl, $shr, $sshl, $sshr)
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index <SigSpec> port(outer_shift, \A) === inner_y
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set outer_b port(outer_shift, \B)
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set outer_y port(outer_shift, \Y)
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endmatch
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code inner_a inner_b inner_y outer_b outer_y
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bool inner_is_left = inner_shift->type.in($shl, $sshl);
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bool outer_is_left = outer_shift->type.in($shl, $sshl);
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bool same_direction = (inner_is_left == outer_is_left);
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// Unset all ports
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inner_shift->unsetPort(\A);
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inner_shift->unsetPort(\B);
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inner_shift->unsetPort(\Y);
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outer_shift->unsetPort(\A);
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outer_shift->unsetPort(\B);
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outer_shift->unsetPort(\Y);
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Cell *cell = outer_shift;
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// Create combined shift amount
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int combined_width = max(GetSize(inner_b), GetSize(outer_b)) + 1;
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Wire *combined_amt = module->addWire(NEW_ID2, combined_width);
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if (same_direction) {
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// Same direction: b + c
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module->addAdd(NEW_ID2, inner_b, outer_b, combined_amt,
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false, cell->get_src_attribute());
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} else {
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// Mixed direction: b - c
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module->addSub(NEW_ID2, inner_b, outer_b, combined_amt,
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false, cell->get_src_attribute());
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}
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// Reuse outer shift with inner shift's type, original data, and combined amount
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outer_shift->type = inner_shift->type;
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outer_shift->setPort(\A, inner_a);
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outer_shift->setPort(\B, combined_amt);
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outer_shift->setPort(\Y, outer_y);
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outer_shift->setParam(\A_SIGNED, inner_shift->getParam(\A_SIGNED));
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outer_shift->fixup_parameters();
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// Rename for formal
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module->rename(outer_shift, NEW_ID2);
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// Remove inner shift
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autoremove(inner_shift);
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log("combine_shifts pattern in %s: inner=%s (%s), outer=%s (%s)\n",
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log_id(module), log_id(inner_shift), log_id(inner_shift->type),
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log_id(outer_shift), log_id(outer_shift->type));
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did_something = true;
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accept;
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endcode
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@ -0,0 +1,93 @@
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pattern expand_shifts
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//
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// Authored by Akash Levy of Silimate, Inc. under ISC license.
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//
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// Expand shifts across binary operations
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//
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// y = (a OP b) << c ===> y = (a << c) OP (b << c)
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// y = (a OP b) >> c ===> y = (a >> c) OP (b >> c)
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// y = (a OP b) <<< c ===> y = (a <<< c) OP (b <<< c)
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// y = (a OP b) >>> c ===> y = (a >>> c) OP (b >>> c)
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//
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// where OP in {$and, $or, $xor, $add, $sub}
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//
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state <SigSpec> op_a op_b op_y shift_amt shift_y
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match op_gate
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// Select inner binary operation gate
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select op_gate->type.in($and, $or, $xor, $add, $sub)
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set op_a port(op_gate, \A)
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set op_b port(op_gate, \B)
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set op_y port(op_gate, \Y)
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endmatch
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code
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// Fanout of each OP gate Y bit should be 1 (no bit-split)
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if (nusers(op_y) != 2)
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reject;
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endcode
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match shift_gate
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// Select shift gate consuming the OP gate's output
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select shift_gate->type.in($shl, $shr, $sshl, $sshr)
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// Connection: shift gate's A input is the OP gate's output
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index <SigSpec> port(shift_gate, \A) === op_y
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set shift_amt port(shift_gate, \B)
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set shift_y port(shift_gate, \Y)
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endmatch
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code op_a op_b op_y shift_amt shift_y
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// Unset all ports
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shift_gate->unsetPort(\A);
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shift_gate->unsetPort(\B);
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shift_gate->unsetPort(\Y);
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op_gate->unsetPort(\A);
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op_gate->unsetPort(\B);
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op_gate->unsetPort(\Y);
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Cell *cell = shift_gate;
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// Create new intermediate wires
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Wire *new_op_a = module->addWire(NEW_ID2, GetSize(shift_y));
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Wire *new_op_b = module->addWire(NEW_ID2, GetSize(shift_y));
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// Create new shift gates: (a SHIFT c) and (b SHIFT c)
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Cell *new_shift_a = module->addCell(NEW_ID2, shift_gate->type);
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new_shift_a->setPort(\A, op_a);
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new_shift_a->setPort(\B, shift_amt);
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new_shift_a->setPort(\Y, new_op_a);
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new_shift_a->setParam(\A_SIGNED, shift_gate->getParam(\A_SIGNED));
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new_shift_a->setParam(\B_SIGNED, shift_gate->getParam(\B_SIGNED));
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new_shift_a->fixup_parameters();
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new_shift_a->set_src_attribute(cell->get_src_attribute());
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Cell *new_shift_b = module->addCell(NEW_ID2, shift_gate->type);
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new_shift_b->setPort(\A, op_b);
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new_shift_b->setPort(\B, shift_amt);
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new_shift_b->setPort(\Y, new_op_b);
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new_shift_b->setParam(\A_SIGNED, shift_gate->getParam(\A_SIGNED));
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new_shift_b->setParam(\B_SIGNED, shift_gate->getParam(\B_SIGNED));
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new_shift_b->fixup_parameters();
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new_shift_b->set_src_attribute(cell->get_src_attribute());
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// Update OP gate to take shifted inputs and produce final output
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op_gate->setPort(\A, new_op_a);
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op_gate->setPort(\B, new_op_b);
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op_gate->setPort(\Y, shift_y);
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op_gate->fixup_parameters();
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// Rename OP gate for formal
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cell = op_gate;
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module->rename(op_gate, NEW_ID2);
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// Remove original shift gate
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autoremove(shift_gate);
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// Log, fixup, accept
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log("expand_shifts pattern in %s: op=%s (%s), shift=%s (%s)\n", log_id(module), log_id(op_gate), log_id(op_gate->type), log_id(shift_gate), log_id(shift_gate->type));
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did_something = true;
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accept;
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endcode
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@ -0,0 +1,377 @@
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log -header "Same direction SHL: (a << b) << c"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [7:0] a,
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input wire [2:0] b,
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input wire [2:0] c,
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output wire [7:0] x
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);
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assign x = (a << b) << c;
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endmodule
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EOF
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check -assert
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equiv_opt -assert opt_shift -combine
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design -load postopt
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select -assert-count 1 t:$shl
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select -assert-count 1 t:$add
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design -reset
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log -pop
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log -header "Same direction SHR: (a >> b) >> c"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [7:0] a,
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input wire [2:0] b,
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input wire [2:0] c,
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output wire [7:0] x
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);
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assign x = (a >> b) >> c;
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endmodule
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EOF
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check -assert
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equiv_opt -assert opt_shift -combine
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design -load postopt
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select -assert-count 1 t:$shr
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select -assert-count 1 t:$add
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design -reset
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log -pop
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log -header "Same direction SSHR: (a >>> b) >>> c (signed arithmetic)"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire signed [7:0] a,
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input wire [2:0] b,
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input wire [2:0] c,
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output wire signed [7:0] x
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);
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assign x = (a >>> b) >>> c;
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endmodule
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EOF
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check -assert
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equiv_opt -assert opt_shift -combine
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design -load postopt
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select -assert-count 1 t:$sshr
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select -assert-count 1 t:$add
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design -reset
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log -pop
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log -header "Negative case: fanout from intermediate wire prevents combining"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [7:0] a,
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input wire [2:0] b,
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input wire [2:0] c,
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output wire [7:0] m,
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output wire [7:0] x
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);
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assign m = a << b;
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assign x = m << c;
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endmodule
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EOF
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check -assert
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equiv_opt -assert opt_shift -combine
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design -load postopt
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select -assert-count 2 t:$shl
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select -assert-count 0 t:$add
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design -reset
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log -pop
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log -header "Triple chain: ((a << b) << c) << d"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [7:0] a,
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input wire [2:0] b,
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input wire [2:0] c,
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input wire [2:0] d,
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output wire [7:0] x
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);
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assign x = ((a << b) << c) << d;
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endmodule
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EOF
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check -assert
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equiv_opt -assert opt_shift -combine
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design -load postopt
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select -assert-count 1 t:$shl
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select -assert-count 2 t:$add
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design -reset
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log -pop
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log -header "Mixed direction: (a << b) >> c"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire [7:0] a,
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input wire [2:0] b,
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input wire [2:0] c,
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output wire [7:0] x
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);
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assign x = (a << b) >> c;
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endmodule
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EOF
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check -assert
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opt_shift -combine
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select -assert-count 1 t:$shl
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select -assert-count 0 t:$shr
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select -assert-count 1 t:$sub
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design -reset
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log -pop
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|
||||
|
||||
|
||||
log -header "Mixed direction: (a >> b) << c"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [7:0] a,
|
||||
input wire [2:0] b,
|
||||
input wire [2:0] c,
|
||||
output wire [7:0] x
|
||||
);
|
||||
assign x = (a >> b) << c;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
opt_shift -combine
|
||||
select -assert-count 0 t:$shl
|
||||
select -assert-count 1 t:$shr
|
||||
select -assert-count 1 t:$sub
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "Cross-type same direction: $shr then $sshr"
|
||||
log -push
|
||||
design -reset
|
||||
read_rtlil <<EOF
|
||||
autoidx 1
|
||||
module \top
|
||||
wire width 8 input 1 \a
|
||||
wire width 3 input 2 \b
|
||||
wire width 3 input 3 \c
|
||||
wire width 8 output 4 \x
|
||||
wire width 8 \t
|
||||
cell $shr \shr_cell
|
||||
parameter \A_SIGNED 0
|
||||
parameter \B_SIGNED 0
|
||||
parameter \A_WIDTH 8
|
||||
parameter \B_WIDTH 3
|
||||
parameter \Y_WIDTH 8
|
||||
connect \A \a
|
||||
connect \B \b
|
||||
connect \Y \t
|
||||
end
|
||||
cell $sshr \sshr_cell
|
||||
parameter \A_SIGNED 1
|
||||
parameter \B_SIGNED 0
|
||||
parameter \A_WIDTH 8
|
||||
parameter \B_WIDTH 3
|
||||
parameter \Y_WIDTH 8
|
||||
connect \A \t
|
||||
connect \B \c
|
||||
connect \Y \x
|
||||
end
|
||||
end
|
||||
EOF
|
||||
check -assert
|
||||
opt_shift -combine
|
||||
select -assert-count 1 t:$shr
|
||||
select -assert-count 0 t:$sshr
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "Cross-type same direction: $sshr then $shr"
|
||||
log -push
|
||||
design -reset
|
||||
read_rtlil <<EOF
|
||||
autoidx 1
|
||||
module \top
|
||||
wire width 8 input 1 \a
|
||||
wire width 3 input 2 \b
|
||||
wire width 3 input 3 \c
|
||||
wire width 8 output 4 \x
|
||||
wire width 8 \t
|
||||
cell $sshr \sshr_cell
|
||||
parameter \A_SIGNED 1
|
||||
parameter \B_SIGNED 0
|
||||
parameter \A_WIDTH 8
|
||||
parameter \B_WIDTH 3
|
||||
parameter \Y_WIDTH 8
|
||||
connect \A \a
|
||||
connect \B \b
|
||||
connect \Y \t
|
||||
end
|
||||
cell $shr \shr_cell
|
||||
parameter \A_SIGNED 0
|
||||
parameter \B_SIGNED 0
|
||||
parameter \A_WIDTH 8
|
||||
parameter \B_WIDTH 3
|
||||
parameter \Y_WIDTH 8
|
||||
connect \A \t
|
||||
connect \B \c
|
||||
connect \Y \x
|
||||
end
|
||||
end
|
||||
EOF
|
||||
check -assert
|
||||
opt_shift -combine
|
||||
select -assert-count 0 t:$shr
|
||||
select -assert-count 1 t:$sshr
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "Cross-type mixed direction: $sshr then $shl"
|
||||
log -push
|
||||
design -reset
|
||||
read_rtlil <<EOF
|
||||
autoidx 1
|
||||
module \top
|
||||
wire width 8 input 1 \a
|
||||
wire width 3 input 2 \b
|
||||
wire width 3 input 3 \c
|
||||
wire width 8 output 4 \x
|
||||
wire width 8 \t
|
||||
cell $sshr \sshr_cell
|
||||
parameter \A_SIGNED 1
|
||||
parameter \B_SIGNED 0
|
||||
parameter \A_WIDTH 8
|
||||
parameter \B_WIDTH 3
|
||||
parameter \Y_WIDTH 8
|
||||
connect \A \a
|
||||
connect \B \b
|
||||
connect \Y \t
|
||||
end
|
||||
cell $shl \shl_cell
|
||||
parameter \A_SIGNED 0
|
||||
parameter \B_SIGNED 0
|
||||
parameter \A_WIDTH 8
|
||||
parameter \B_WIDTH 3
|
||||
parameter \Y_WIDTH 8
|
||||
connect \A \t
|
||||
connect \B \c
|
||||
connect \Y \x
|
||||
end
|
||||
end
|
||||
EOF
|
||||
check -assert
|
||||
opt_shift -combine
|
||||
select -assert-count 0 t:$shl
|
||||
select -assert-count 1 t:$sshr
|
||||
select -assert-count 1 t:$sub
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "Cross-type mixed direction: $shl then $sshr"
|
||||
log -push
|
||||
design -reset
|
||||
read_rtlil <<EOF
|
||||
autoidx 1
|
||||
module \top
|
||||
wire width 8 input 1 \a
|
||||
wire width 3 input 2 \b
|
||||
wire width 3 input 3 \c
|
||||
wire width 8 output 4 \x
|
||||
wire width 8 \t
|
||||
cell $shl \shl_cell
|
||||
parameter \A_SIGNED 0
|
||||
parameter \B_SIGNED 0
|
||||
parameter \A_WIDTH 8
|
||||
parameter \B_WIDTH 3
|
||||
parameter \Y_WIDTH 8
|
||||
connect \A \a
|
||||
connect \B \b
|
||||
connect \Y \t
|
||||
end
|
||||
cell $sshr \sshr_cell
|
||||
parameter \A_SIGNED 1
|
||||
parameter \B_SIGNED 0
|
||||
parameter \A_WIDTH 8
|
||||
parameter \B_WIDTH 3
|
||||
parameter \Y_WIDTH 8
|
||||
connect \A \t
|
||||
connect \B \c
|
||||
connect \Y \x
|
||||
end
|
||||
end
|
||||
EOF
|
||||
check -assert
|
||||
opt_shift -combine
|
||||
select -assert-count 1 t:$shl
|
||||
select -assert-count 0 t:$sshr
|
||||
select -assert-count 1 t:$sub
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "1-bit operands: (a << b) << c"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire a,
|
||||
input wire [2:0] b,
|
||||
input wire [2:0] c,
|
||||
output wire [7:0] x
|
||||
);
|
||||
assign x = (a << b) << c;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
equiv_opt -assert opt_shift -combine
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$shl
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "Constant shift amounts: (a << 3) << 2"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [7:0] a,
|
||||
output wire [7:0] x
|
||||
);
|
||||
assign x = (a << 3) << 2;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
equiv_opt -assert opt_shift -combine
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$shl
|
||||
select -assert-count 1 t:$add
|
||||
design -reset
|
||||
log -pop
|
||||
|
|
@ -0,0 +1,278 @@
|
|||
log -header "SHL across AND: (a & b) << c"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [7:0] a,
|
||||
input wire [7:0] b,
|
||||
input wire [2:0] c,
|
||||
output wire [7:0] x
|
||||
);
|
||||
assign x = (a & b) << c;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
equiv_opt -assert opt_shift -expand
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$and
|
||||
select -assert-count 2 t:$shl
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "SHL across OR: (a | b) << c"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [7:0] a,
|
||||
input wire [7:0] b,
|
||||
input wire [2:0] c,
|
||||
output wire [7:0] x
|
||||
);
|
||||
assign x = (a | b) << c;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
equiv_opt -assert opt_shift -expand
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$or
|
||||
select -assert-count 2 t:$shl
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "SHL across XOR: (a ^ b) << c"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [7:0] a,
|
||||
input wire [7:0] b,
|
||||
input wire [2:0] c,
|
||||
output wire [7:0] x
|
||||
);
|
||||
assign x = (a ^ b) << c;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
equiv_opt -assert opt_shift -expand
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$xor
|
||||
select -assert-count 2 t:$shl
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "SHL across ADD: (a + b) << c"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [7:0] a,
|
||||
input wire [7:0] b,
|
||||
input wire [2:0] c,
|
||||
output wire [7:0] x
|
||||
);
|
||||
assign x = (a + b) << c;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
equiv_opt -assert opt_shift -expand
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-count 2 t:$shl
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "SHL across SUB: (a - b) << c"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [7:0] a,
|
||||
input wire [7:0] b,
|
||||
input wire [2:0] c,
|
||||
output wire [7:0] x
|
||||
);
|
||||
assign x = (a - b) << c;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
equiv_opt -assert opt_shift -expand
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$sub
|
||||
select -assert-count 2 t:$shl
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "SHR across AND: (a & b) >> c"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [7:0] a,
|
||||
input wire [7:0] b,
|
||||
input wire [2:0] c,
|
||||
output wire [7:0] x
|
||||
);
|
||||
assign x = (a & b) >> c;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
equiv_opt -assert opt_shift -expand
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$and
|
||||
select -assert-count 2 t:$shr
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "SHR across XOR: (a ^ b) >> c"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [7:0] a,
|
||||
input wire [7:0] b,
|
||||
input wire [2:0] c,
|
||||
output wire [7:0] x
|
||||
);
|
||||
assign x = (a ^ b) >> c;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
equiv_opt -assert opt_shift -expand
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$xor
|
||||
select -assert-count 2 t:$shr
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "SSHR (arithmetic right shift) across AND: signed (a & b) >>> c"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire signed [7:0] a,
|
||||
input wire signed [7:0] b,
|
||||
input wire [2:0] c,
|
||||
output wire signed [7:0] x
|
||||
);
|
||||
assign x = (a & b) >>> c;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
equiv_opt -assert opt_shift -expand
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$and
|
||||
select -assert-count 2 t:$sshr
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "Negative case: fanout from intermediate wire prevents expansion"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [7:0] a,
|
||||
input wire [7:0] b,
|
||||
input wire [2:0] c,
|
||||
output wire [7:0] m,
|
||||
output wire [7:0] x
|
||||
);
|
||||
assign m = a & b;
|
||||
assign x = m << c;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
equiv_opt -assert opt_shift -expand
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$and
|
||||
select -assert-count 1 t:$shl
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "1-bit operands: (a & b) << c"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire a,
|
||||
input wire b,
|
||||
input wire [2:0] c,
|
||||
output wire [7:0] x
|
||||
);
|
||||
assign x = (a & b) << c;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
equiv_opt -assert opt_shift -expand
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$and
|
||||
select -assert-count 2 t:$shl
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "Nested: ((a | b) << c) ^ d"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [7:0] a,
|
||||
input wire [7:0] b,
|
||||
input wire [2:0] c,
|
||||
input wire [7:0] d,
|
||||
output wire [7:0] x
|
||||
);
|
||||
assign x = ((a | b) << c) ^ d;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
equiv_opt -assert opt_shift -expand
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$xor
|
||||
select -assert-count 1 t:$or
|
||||
select -assert-count 2 t:$shl
|
||||
design -reset
|
||||
log -pop
|
||||
|
||||
|
||||
|
||||
log -header "Chained shifts: ((a + b) << c) << d"
|
||||
log -push
|
||||
design -reset
|
||||
read_verilog <<EOF
|
||||
module top (
|
||||
input wire [7:0] a,
|
||||
input wire [7:0] b,
|
||||
input wire [2:0] c,
|
||||
input wire [2:0] d,
|
||||
output wire [7:0] x
|
||||
);
|
||||
assign x = ((a + b) << c) << d;
|
||||
endmodule
|
||||
EOF
|
||||
check -assert
|
||||
equiv_opt -assert opt_shift -expand
|
||||
design -load postopt
|
||||
select -assert-count 1 t:$add
|
||||
select -assert-count 4 t:$shl
|
||||
design -reset
|
||||
log -pop
|
||||
Loading…
Reference in New Issue