 nella
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ec2b287c1e
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Merge pull request #6150 from YosysHQ/nella/rm-unused-ports
rmports: remove output ports unused by all instances [sc-799]
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2026-09-22 13:01:17 +00:00 |
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 nella
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90e281a964
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Reject abc9 boxes without an input or an output.
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2026-09-21 16:58:03 +02:00 |
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nella
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315f8194a0
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Don't mark cells w no unput as boxes.
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2026-09-21 16:58:03 +02:00 |
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nella
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d8d54fafd7
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Mark cells as imported correctly.
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2026-09-21 16:57:58 +02:00 |
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nella
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c3c5388ed9
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Clean up after bufnorm.
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2026-09-21 16:57:53 +02:00 |
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nella
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5726f981fa
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Keep keep wires in abc.
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2026-09-21 16:57:41 +02:00 |
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nella
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c0f8629f7c
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Keep scopeinfo.
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2026-09-21 16:57:41 +02:00 |
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nella
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859b245eb5
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Don't divide by zero with zero delays.
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2026-09-21 16:57:41 +02:00 |
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nella
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e7dd15a4b8
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Clear options per invocation.
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2026-09-21 16:57:26 +02:00 |
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nella
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ce87b2fb3d
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Expect abc error.
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2026-09-21 16:39:09 +02:00 |
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nella
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edb9422be5
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Rm undeclared cell type test.
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2026-09-21 16:33:47 +02:00 |
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nella
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ba063d0af2
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Skip failing tests.
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2026-09-21 16:33:47 +02:00 |
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nella
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b60492b203
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Repro tie box, portarcs, read_liberty.
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2026-09-21 16:33:47 +02:00 |
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nella
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fb74fe275d
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Repro dropped keep and scopeinfo.
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2026-09-21 16:33:47 +02:00 |
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nella
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aa19d5ea02
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Repro bufnorm leftovers.
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2026-09-21 16:33:47 +02:00 |
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nella
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03e33b4cd6
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Repro option accumulation.
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2026-09-21 16:33:47 +02:00 |
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nella
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ba581d42d1
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Add issue regressions.
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2026-09-21 16:33:47 +02:00 |
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nella
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fd766716f4
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Generate librelane ABC scripts.
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2026-09-21 16:33:47 +02:00 |
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nella
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f3934d1ed8
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Add librelane spm tests.
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2026-09-21 16:33:47 +02:00 |
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nella
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5a11d677dd
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Test memory macro.
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2026-09-21 16:33:47 +02:00 |
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nella
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22b5ab620c
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Port OpenROAD syn cases.
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2026-09-21 16:33:47 +02:00 |
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nella
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9a7221f103
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Port OpenROAD cut tests.
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2026-09-21 16:33:47 +02:00 |
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nella
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7649fac442
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Test hierarchy and selections.
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2026-09-21 16:33:47 +02:00 |
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nella
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666df5e9c8
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Test boundary cells.
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2026-09-21 16:33:47 +02:00 |
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nella
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ed8b0bf9f7
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Test port corner cases.
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2026-09-21 16:33:47 +02:00 |
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nella
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8955e0fe7a
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Add abc_new tests.
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2026-09-21 16:33:47 +02:00 |
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nella
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9e8f12b9b3
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Merge pull request #6207 from YosysHQ/nella/xilinx-rdfirst-xc7
xilinx: fix BRAM mapping for negedge port next to READ_FIRST port [sc-917]
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2026-09-16 13:14:35 +00:00 |
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nella
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a651db986a
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xilinx: Drop READ_FIRST erratum on 7 series.
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2026-09-16 09:14:50 +02:00 |
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 Lofty
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415dfc0960
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xaiger2: add testcase from #4349
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2026-09-16 08:13:23 +01:00 |
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nella
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0edda7a3ab
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Merge pull request #6201 from YosysHQ/nella/check-internal-celltypes
check: reject unknown internal cell types [sc-915]
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2026-09-15 11:52:15 +00:00 |
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 Lofty
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d85872386a
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Merge pull request #6174 from YosysHQ/lofty/abc-refactor-16
abc9: migrate to write_xaiger2
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2026-09-14 16:25:07 +00:00 |
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 Miodrag Milanović
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f04d70bd9b
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Merge pull request #6200 from YosysHQ/mmicko/heredoc
Use <inlined> for heredoc input filename
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2026-09-14 14:50:38 +00:00 |
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nella
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76213a5d4c
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Reject unknown internal cell types in check and hierarchy -check.
A $-prefixed cell type must be a known cell type or a module in the
design. check reports it as a problem, hierarchy -check errors.
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2026-09-14 13:50:09 +02:00 |
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Miodrag Milanovic
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5cdba4fbd7
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Update tests to reflect change to <inlined>
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2026-09-14 10:35:11 +02:00 |
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nella
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333d4b8bb0
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rmports: only rely on top attr.
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2026-09-14 10:21:17 +02:00 |
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 Emil J. Tywoniak
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60a7f254f8
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tests: rebless blif gatesi cell order
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2026-09-10 18:16:57 +02:00 |
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Emil J. Tywoniak
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cc9d6389d6
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tests: rebless gatemate cell counts
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2026-09-10 18:16:57 +02:00 |
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Miodrag Milanović
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3a82894842
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Merge pull request #6100 from YosysHQ/mmicko/test_verific
tests: Explicitly run tests without and with Verific where applicable
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2026-09-10 10:07:07 +00:00 |
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Miodrag Milanović
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ae86bbb130
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Revert "Temporarily revert #6101 and #6077"
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2026-09-10 09:09:13 +02:00 |
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 Emil J
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370a53acf8
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Merge pull request #6169 from YosysHQ/emil/check-process-conflicts
check: detect process-driver conflicts
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2026-09-09 16:52:20 +00:00 |
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Emil J
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5274c96506
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Merge pull request #6161 from YosysHQ/emil/remove-dead-bindings
rtlil: remove dead verilog bindings
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2026-09-09 16:51:35 +00:00 |
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Miodrag Milanovic
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9f75ca1f98
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Release version 0.69
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2026-09-09 07:26:44 +02:00 |
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Miodrag Milanović
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f1442ce42e
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Merge pull request #6182 from YosysHQ/lofty/revert-read_xaiger2
Temporarily revert #6101 and #6077
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2026-09-08 04:53:08 +00:00 |
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Lofty
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51583d854a
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Revert "Merge pull request #6077 from YosysHQ/lofty/abc-refactor-8"
This reverts commit fd6367405e, reversing
changes made to 0f2bcb94b7.
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2026-09-07 17:29:08 +01:00 |
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nella
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c4b6c19580
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Rank cells on tuple.
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2026-09-04 11:16:24 +02:00 |
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Lofty
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a6790877e4
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fix dsp.ys
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2026-09-03 13:28:38 +01:00 |
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Lofty
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e35d4bcc15
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fix meminit.ys
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2026-09-03 13:24:37 +01:00 |
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nella
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ad5f80bf0d
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Drop replaced box.
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2026-09-03 14:16:31 +02:00 |
|
 Nick Allison
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0bf55a858b
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Merge pull request #6164 from YosysHQ/nick/fix-6151
Adding error cases to formal backends for invalid formal cells
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2026-09-02 14:42:28 +00:00 |
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Emil J. Tywoniak
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d8a4bf0c82
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check: detect process-driver conflicts
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2026-09-02 15:28:01 +02:00 |
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