Merge pull request #6200 from YosysHQ/mmicko/heredoc

Use <inlined> for heredoc input filename

kernel/register.cc

@@ -485,8 +485,7 @@ void Frontend::extra_args(std::istream *&f, std::string &filename, std::vector<s
 			if (filename.size() <= 2)
 				log_error("Missing EOT marker in here document!\n");
 			std::string eot_marker = filename.substr(2);
-			if (Frontend::current_script_file == nullptr)
-				filename = "<stdin>";
+			filename = (Frontend::current_script_file == nullptr) ?  "<stdin>" : "<inlined>";
 			last_here_document.clear();
 			while (1) {
 				std::string buffer;

tests/arch/ice40/ice40_wrapcarry.ys

@@ -50,5 +50,5 @@ select -assert-count 0 t:* t:$__ICE40_CARRY_WRAPPER %d
 select -assert-count 1 a:keep=1 a:SB_CARRY.\foo=bar %i a:SB_CARRY.\answer=42 %i a:SB_LUT4.\blah=blah %i a:SB_LUT4.\answer=43 %i
 
 ice40_wrapcarry -unwrap
-select -assert-count 1 c:carry a:src=<<EOT:3.11-8.3 %i a:keep=0 %i a:foo=bar %i a:answer=42 %i
-select -assert-count 1 c:adder a:src=<<EOT:12.4-18.3 %i a:keep=1 %i a:blah=blah %i a:answer=43 %i
+select -assert-count 1 c:carry a:src=<inlined>:3.11-8.3 %i a:keep=0 %i a:foo=bar %i a:answer=42 %i
+select -assert-count 1 c:adder a:src=<inlined>:12.4-18.3 %i a:keep=1 %i a:blah=blah %i a:answer=43 %i

tests/various/mem2reg.ys

@@ -9,6 +9,6 @@ EOT
 
 proc
 cd top
-select -assert-count 1 m:data1 a:src=<<EOT:4.43-4.48 %i
-select -assert-count 2 w:data2[*] a:src=<<EOT:5.41-5.46 %i
+select -assert-count 1 m:data1 a:src=<inlined>:4.43-4.48 %i
+select -assert-count 2 w:data2[*] a:src=<inlined>:5.41-5.46 %i
 select -assert-none a:mem2reg

tests/various/primitives.ys

@@ -8,9 +8,9 @@ xor (y[4], a, b);
 xnor (y[5], a, b);
 endmodule
 EOT
-select -assert-count 1 t:$and a:src=<<EOT:2.4-2.17 %i
-select -assert-count 1 t:$and a:src=<<EOT:3.5-3.18 %i
-select -assert-count 1 t:$or a:src=<<EOT:4.3-4.16 %i
-select -assert-count 1 t:$or a:src=<<EOT:5.4-5.17 %i
-select -assert-count 1 t:$xor a:src=<<EOT:6.4-6.17 %i
-select -assert-count 1 t:$xor a:src=<<EOT:7.5-7.18 %i
+select -assert-count 1 t:$and a:src=<inlined>:2.4-2.17 %i
+select -assert-count 1 t:$and a:src=<inlined>:3.5-3.18 %i
+select -assert-count 1 t:$or a:src=<inlined>:4.3-4.16 %i
+select -assert-count 1 t:$or a:src=<inlined>:5.4-5.17 %i
+select -assert-count 1 t:$xor a:src=<inlined>:6.4-6.17 %i
+select -assert-count 1 t:$xor a:src=<inlined>:7.5-7.18 %i

tests/various/printattr.ys

@@ -1,5 +1,5 @@
 logger -expect log ".*cells_not_processed=[01]* .*" 1
-logger -expect log ".*src=.<<EOT:1\.1-9\.10. .*" 1
+logger -expect log ".*src=.<inlined>:1\.1-9\.10. .*" 1
 read_verilog <<EOT
 module mux2(a, b, s, y);
 	input a, b, s;

tests/various/rename_scramble_name.ys

@@ -28,4 +28,4 @@ hierarchy -top top
 rename -seed 2 -scramble-name c:bar
 select -assert-none c:bar
 select -assert-count 1 c:$_*_
-select -assert-none c:$_*_ w:* foo/c:$add$<<EOF:2$1 %% %n
+select -assert-none c:$_*_ w:* foo/c:$add$<inlined>:2$1 %% %n

tests/various/rename_unescape.ys

@@ -27,7 +27,7 @@ select -assert-count 1 w:$e
 # Colliding with keyword
 select -assert-count 1 w:wire
 # Don't touch internal names
-select -assert-count 1 w:$add$<<EOF:*$1_Y
+select -assert-count 1 w:$add$<inlined>:*$1_Y
 
 rename -unescape
 
@@ -38,7 +38,7 @@ select -assert-count 1 w:d_
 select -assert-count 1 w:d__1
 select -assert-count 1 w:_e
 select -assert-count 1 w:wire_
-select -assert-count 1 w:$add$<<EOF:*$1_Y
+select -assert-count 1 w:$add$<inlined>:*$1_Y
 
 # Ports are updated during rename
 design -reset

tests/various/src.ys

@@ -1,5 +1,5 @@
-logger -expect warning "wire '\\o' is assigned in a block at <<EOT:2.11-2.17" 1
-logger -expect warning "wire '\\p' is assigned in a block at <<EOT:3.11-3.16" 1
+logger -expect warning "wire '\\o' is assigned in a block at <inlined>:2.11-2.17" 1
+logger -expect warning "wire '\\p' is assigned in a block at <inlined>:3.11-3.16" 1
 read_verilog <<EOT
 module top(input i, output o, p);
 always @* o <= i;

tests/verilog/constparser_f.ys

@@ -1,4 +1,4 @@
-logger -expect prefix-error "<<EOT:2: ERROR: Digit larger than 1 used in in base-2 constant." 1
+logger -expect prefix-error "<inlined>:2: ERROR: Digit larger than 1 used in in base-2 constant." 1
 read_verilog <<EOT
 module test (y);
     output signed [2:0] y = 1'bf;

tests/verilog/constparser_g.ys

@@ -1,4 +1,4 @@
-logger -expect prefix-error "<<EOT:2: ERROR: syntax error, unexpected invalid token, expecting TOK_BASED_CONSTVAL" 1
+logger -expect prefix-error "<inlined>:2: ERROR: syntax error, unexpected invalid token, expecting TOK_BASED_CONSTVAL" 1
 read_verilog <<EOT
 module test (y);
     output signed [2:0] y = 1'bg;