fix dsp.ys

2026-09-05 11:35:20 +02:00 · 2026-09-03 13:28:38 +01:00
parent e35d4bcc15
commit a6790877e4
1 changed files with 1 additions and 1 deletions
@@ -114,7 +114,7 @@ always @(posedge clk) begin
 end
 endmodule
 EOF
-read_verilog +/quicklogic/qlf_k6n10f/dsp_sim.v
+techmap -autoproc -map +/quicklogic/qlf_k6n10f/dsp_sim.v
 hierarchy -top testbench
 proc
 async2sync