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Author SHA1 Message Date
nella c3c5388ed9 Clean up after bufnorm. 2026-09-21 16:57:53 +02:00
nella 5726f981fa Keep keep wires in abc. 2026-09-21 16:57:41 +02:00
nella c0f8629f7c Keep scopeinfo. 2026-09-21 16:57:41 +02:00
nella 859b245eb5 Don't divide by zero with zero delays. 2026-09-21 16:57:41 +02:00
nella e7dd15a4b8 Clear options per invocation. 2026-09-21 16:57:26 +02:00
nella ce87b2fb3d Expect abc error. 2026-09-21 16:39:09 +02:00
nella edb9422be5 Rm undeclared cell type test. 2026-09-21 16:33:47 +02:00
nella ba063d0af2 Skip failing tests. 2026-09-21 16:33:47 +02:00
nella b60492b203 Repro tie box, portarcs, read_liberty. 2026-09-21 16:33:47 +02:00
nella fb74fe275d Repro dropped keep and scopeinfo. 2026-09-21 16:33:47 +02:00
nella aa19d5ea02 Repro bufnorm leftovers. 2026-09-21 16:33:47 +02:00
nella 03e33b4cd6 Repro option accumulation. 2026-09-21 16:33:47 +02:00
nella ba581d42d1 Add issue regressions. 2026-09-21 16:33:47 +02:00
nella fd766716f4 Generate librelane ABC scripts. 2026-09-21 16:33:47 +02:00
nella f3934d1ed8 Add librelane spm tests. 2026-09-21 16:33:47 +02:00
nella 5a11d677dd Test memory macro. 2026-09-21 16:33:47 +02:00
nella 22b5ab620c Port OpenROAD syn cases. 2026-09-21 16:33:47 +02:00
nella 9a7221f103 Port OpenROAD cut tests. 2026-09-21 16:33:47 +02:00
nella 7649fac442 Test hierarchy and selections. 2026-09-21 16:33:47 +02:00
nella 666df5e9c8 Test boundary cells. 2026-09-21 16:33:47 +02:00
nella ed8b0bf9f7 Test port corner cases. 2026-09-21 16:33:47 +02:00
nella 8955e0fe7a Add abc_new tests. 2026-09-21 16:33:47 +02:00
Miodrag Milanović 7b5eba489c Merge pull request #6229 from YosysHQ/micko/update_abc 
Update ABC as per 2026-09-21
 2026-09-21 13:54:39 +00:00
Miodrag Milanovic f3159c72cb Update ABC as per 2026-09-21 2026-09-21 13:53:37 +02:00
N. Engelhardt 950ac95e85 Merge pull request #6226 from YosysHQ/krys/contributing_formatting 
contributing.rst: Fixing up formatting
 2026-09-21 08:33:10 +00:00
N. Engelhardt 2d2f2cfede Merge pull request #6160 from YosysHQ/itsaflower-patch-2 
Add AI policy
 2026-09-21 08:33:02 +00:00
Krystine Sherwin 1cf1c5f02d contributing.rst: Fixing up formatting 2026-09-21 20:03:30 +12:00
Krystine Sherwin 92d6ae7fb7 docs: Link to interim LLM policy 2026-09-21 20:03:30 +12:00
itsaflower 64233b1cc1 Update CONTRIBUTING.md 2026-09-21 20:03:30 +12:00
Catherine 9ff27d29c6 Merge pull request #6212 from YosysHQ/mmicko/yosys_python_executable 
cmake: do not alter name in yosys_python_executable
 2026-09-20 14:44:58 +00:00
Miodrag Milanović f0b945f63c Merge pull request #6213 from YosysHQ/mmicko/shutdown_win 
Execute clean shutdown on windows as well
 2026-09-18 06:25:07 +00:00
Miodrag Milanovic 656f62b337 Execute clean shutdown on windows as well 2026-09-18 08:06:51 +02:00
Miodrag Milanovic cdee781597 cmake: do not alter name in yosys_python_executable 2026-09-17 12:06:07 +02:00
Miodrag Milanović 2e7d8006da Merge pull request #6211 from YosysHQ/mmicko/abc_update 
Update ABC as per 2026-09-17
 2026-09-17 06:58:35 +00:00
Miodrag Milanovic ff67a82a13 Update ABC as per 2026-09-17 2026-09-17 08:38:40 +02:00
Emil J 150c32b03e Merge pull request #6154 from YosysHQ/emil/liberty-filter 
liberty: add filtering for things we need
 2026-09-16 16:44:09 +00:00
Emil J. Tywoniak 91ac95c2b4 libparse: overwrite cache whenever old filter doesn't cover new filter 2026-09-16 18:21:46 +02:00
nella 9e8f12b9b3 Merge pull request #6207 from YosysHQ/nella/xilinx-rdfirst-xc7 
xilinx: fix BRAM mapping for negedge port next to READ_FIRST port [sc-917]
 2026-09-16 13:14:35 +00:00
Lofty 92f43919b3 Merge pull request #6206 from YosysHQ/lofty/add-xaiger2-test 
xaiger2: add testcase from #4349
 2026-09-16 13:07:30 +00:00
Emil J d5e9476d2b Merge pull request #6208 from YosysHQ/emil/nix-macos-symlink-share 
yosys: fix share path on MacOS when behind a symlink
 2026-09-16 13:04:27 +00:00
Emil J. Tywoniak 716ee4d47a yosys: fix share path on MacOS when behind a symlink 2026-09-16 13:57:26 +02:00
nella a651db986a xilinx: Drop READ_FIRST erratum on 7 series. 2026-09-16 09:14:50 +02:00
Lofty 415dfc0960 xaiger2: add testcase from #4349 2026-09-16 08:13:23 +01:00
nella 0edda7a3ab Merge pull request #6201 from YosysHQ/nella/check-internal-celltypes 
check: reject unknown internal cell types [sc-915]
 2026-09-15 11:52:15 +00:00
Lofty d85872386a Merge pull request #6174 from YosysHQ/lofty/abc-refactor-16 
abc9: migrate to write_xaiger2
 2026-09-14 16:25:07 +00:00
Miodrag Milanović f04d70bd9b Merge pull request #6200 from YosysHQ/mmicko/heredoc 
Use <inlined> for heredoc input filename
 2026-09-14 14:50:38 +00:00
Emil J a9888845d2 Merge pull request #6194 from YosysHQ/emil/abc-module-and-clkdomain-par 
abc: module and clock domain parallelism, always
 2026-09-14 13:29:38 +00:00
nella 76213a5d4c Reject unknown internal cell types in check and hierarchy -check. 
A $-prefixed cell type must be a known cell type or a module in the
design. check reports it as a problem, hierarchy -check errors.
 2026-09-14 13:50:09 +02:00
nella 77bca709d4 Declare synth_fabulous pad cells as blackboxes. 
iopadmap inserted $__FABULOUS_* cells with no module, so their port
directions were unknown to later passes. Read with -icells so the module
names match the cell types.
 2026-09-14 13:50:09 +02:00
Emil J. TywoniakandJakub Michalski 72b30b1820 abc: dispatch modules in cell count order 
Co-authored-by: Jakub Michalski <[email protected]>
 2026-09-14 12:52:10 +02:00