Declare synth_fabulous pad cells as blackboxes.

iopadmap inserted $__FABULOUS_* cells with no module, so their port
directions were unknown to later passes. Read with -icells so the module
names match the cell types.

techlibs/fabulous/CMakeLists.txt

@@ -31,4 +31,5 @@ yosys_pass(synth_fabulous
 	DATA_DIR
 		fabulous
 	DATA_FILES
+		cells_bb.v
 )

techlibs/fabulous/cells_bb.v

@@ -0,0 +1,18 @@
+// Pad cells inserted by synth_fabulous via iopadmap.
+// Mapped to fabric primitives by a user supplied -extra-map.
+
+(* blackbox *)
+module \$__FABULOUS_IBUF (input PAD, output OUT);
+endmodule
+
+(* blackbox *)
+module \$__FABULOUS_OBUF (output PAD, input IN);
+endmodule
+
+(* blackbox *)
+module \$__FABULOUS_TBUF (output PAD, input IN, input EN);
+endmodule
+
+(* blackbox *)
+module \$__FABULOUS_IOBUF (inout PAD, output OUT, input IN, input EN);
+endmodule

techlibs/fabulous/synth_fabulous.cc

@@ -274,6 +274,7 @@ struct SynthPass : public ScriptPass {
 
 	void script() override
 	{
+		run("read_verilog -icells -lib +/fabulous/cells_bb.v");
 		if (help_mode) {
 			run("read_verilog -lib <extra_plib.v>", "(for each -extra-plib)");
 		} else