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abc: dispatch modules in cell count order

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Co-authored-by: Jakub Michalski <[email protected]>
This commit is contained in:
Emil J. Tywoniak
2026-09-14 12:52:10 +02:00
co-authored by Jakub Michalski
parent 5a81ce51c0
commit 72b30b1820
1 changed files with 13 additions and 5 deletions
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passes/techmap/abc.cc
+13 -5
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@@ -2411,13 +2411,21 @@ struct AbcPass : public Pass {
std::exception_ptr error;
try {
for (auto mod : design->selected_modules())
{
if (mod->processes.size() > 0) {
// Process modules from the largest to the smallest. This improves
// the runtime when module sizes are varied, by avoiding the case
// where some large module is picked last
std::vector<RTLIL::Module*> sorted_modules;
for (auto mod : design->selected_modules()) {
if (mod->processes.empty())
sorted_modules.push_back(mod);
else
log("Skipping module %s as it contains processes.\n", mod);
continue;
}
}
std::stable_sort(sorted_modules.begin(), sorted_modules.end(),
[](RTLIL::Module *a, RTLIL::Module *b) { return GetSize(a->cells_) > GetSize(b->cells_); });
for (auto mod : sorted_modules)
{
std::shared_ptr<AbcModuleData> module_data = std::make_shared<AbcModuleData>();
module_data->module = mod;
AbcSigMap &assign_map = module_data->assign_map;