luke
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
17,896 Commits 137 Branches 66 Tags 47 MiB
Commit Graph

17896 Commits

Author SHA1 Message Date
AdvaySingh1 b005f69e27 Added comments in blifparse.cc 2026-02-02 10:15:59 -08:00
AdvaySingh1 9646319098 Fixed source wire to be reset to nullptr so value isn't carried on 2026-02-02 10:10:01 -08:00
AdvaySingh1 15625f56ed Removed cmath arbitrary include 2026-02-02 10:08:41 -08:00
AdvaySingh1 b6c1d2fd27 Merge branch 'main' into nr_cleanup 2026-02-02 09:43:42 -08:00
AdvaySingh1 625d2caeaf ABC: Stylistic abc fixes 2026-02-02 09:41:47 -08:00
Akash Levy 7c70026610 Fix verific issue 2026-02-01 00:16:10 -08:00
Akash Levy bdc9ad9f53 Bump version 2026-01-30 19:29:00 -08:00
Akash Levy 462caedc1c Merge fixups 2026-01-30 18:35:53 -08:00
AdvaySingh1 fc61433faa Reducing verbosity for cell printing 2026-01-30 13:11:36 -08:00
AdvaySingh1 7dab62cb42 ABC cleanup 2026-01-30 12:43:59 -08:00
AdvaySingh1 d7a3b4e312 Removed extraneous readblif knob from abc.cc 2026-01-30 12:42:55 -08:00
AdvaySingh1 3b4574b648 abc.cc node_retention pass cleanup 2026-01-30 12:00:12 -08:00
AdvaySingh1 d7aca59e27 Updated abc.cc and blifparse.cc 2026-01-30 11:22:00 -08:00
Miodrag Milanović ac427a79b0
Merge pull request #5644 from nataliakokoromyti/upstream-linux-perf-unistd 
Add unistd header for Linux
 2026-01-30 08:17:43 +01:00
Miodrag Milanović 382b28acbe
Merge pull request #5648 from YosysHQ/verific_moreopts 
verific: fixed -sv2017 option and added ability to set VHDL standard
 2026-01-30 08:17:19 +01:00
Akash Levy 892ef37b26 Undo 2026-01-29 19:36:36 -08:00
Akash Levy bbdf5042c7 Add PYTHON_INCLUDE_FLAGS 2026-01-29 19:20:46 -08:00
Akash Levy a9cf998f9f Merge from upstream 2026-01-29 17:46:44 -08:00
github-actions[bot] 106f289e31 Bump version 2026-01-30 00:30:58 +00:00
KrystalDelusion 5a4ad6a6d0
Merge pull request #5640 from YosysHQ/krys/fix_mod.py 
Don't use `module mod_name(...)` style in cell libs
 2026-01-30 11:40:07 +13:00
Emil J a68fee1115
Merge pull request #5646 from rocallahan/debug-design_equal 
Dump module details when `design_equal` fails
 2026-01-29 18:57:24 +01:00
Miodrag Milanovic b70f527c67 verific: fixed -sv2017 option and added ability to set VHDL standard if applicable 2026-01-29 10:32:30 +01:00
Miodrag Milanović 6ba8f3dc19
Merge pull request #5647 from YosysHQ/update_abc 
ABC update (MINGW fix)
 2026-01-29 10:12:25 +01:00
Miodrag Milanović 43db5c9488
Merge pull request #5645 from nataliakokoromyti/upstream-verific-mixed-sv-vhdl 
Upstream verific mixed sv vhdl
 2026-01-29 10:12:09 +01:00
Miodrag Milanovic 6007b68e9c ABC update (MINGW fix) 2026-01-29 09:30:12 +01:00
Natalia 8d504ecb48 verific: use MFCU for SV file list 2026-01-29 00:03:28 -08:00
Akash Levy 1dd846022b Fix opt_dff cell naming 2026-01-28 23:36:49 -08:00
Natalia b6c148f84a tests/verific: ensure mixed -f requires VHDL unit 2026-01-28 22:46:10 -08:00
Akash Levy 9f911e3d63 Reorder ff.remove in opt_dff 2026-01-28 20:58:01 -08:00
Akash Levy 5993d2fec8 Remove annoying test case 2026-01-28 19:18:06 -08:00
Akash Levy bb2aadb9ef Merge remote-tracking branch 'upstream/main' 2026-01-28 19:09:56 -08:00
Akash Levy 4e937450b4
Merge pull request #97 from Silimate/reg-rename 
Bug fix for reg_rename pass
 2026-01-28 19:08:26 -08:00
Akash Levy 16087ae931 Merge from upstream 2026-01-28 18:17:50 -08:00
Stan Lee c0a1529eb8 reduce verbosity 2026-01-28 18:05:21 -08:00
Akash Levy e8d27892f0
Merge pull request #96 from Silimate/fanoutbuf_src_attr 
Changed fanoutbuf.cc to include src attributes on buffers connected t…
 2026-01-28 17:50:46 -08:00
Stan Lee 04faedd131 syntax err 2026-01-28 17:40:57 -08:00
Stan Lee dfef18010d shorter lines 2026-01-28 17:20:19 -08:00
Stan Lee 932c4452b5 better working implementation 2026-01-28 17:00:46 -08:00
github-actions[bot] 1f6a13dac7 Bump version 2026-01-29 00:31:03 +00:00
AdvaySingh1 3ce57442de Changed fanoutbuf.cc to include src attributes on buffers connected to input and output wires 2026-01-28 15:33:13 -08:00
Robert O'Callahan 139c38ecfa Dump module details when design_equal fails 2026-01-28 18:32:12 +00:00
nella 8f6c4d40e4
Merge pull request #5623 from YosysHQ/nella/opt-dff-rewrite 
opt_dff restructure.
 2026-01-28 14:41:40 +01:00
Natalia 5a64fe2d91 tests/verific: assert module count explicitly 2026-01-28 04:21:13 -08:00
Natalia 8c2ef89732 tests/verific: import mixed -f list with -all 2026-01-28 04:13:04 -08:00
Natalia 74c601db0f tests/verific: add mixed -f list case 2026-01-28 03:55:42 -08:00
Natalia 6a6e5f0f54 linux_perf: only include unistd on Linux 2026-01-28 03:44:33 -08:00
Natalia 188082551a verific: only use MFCU when VHDL present 2026-01-28 03:37:08 -08:00
Natalia fc2b7c317f linux_perf: include unistd for POSIX I/O 2026-01-28 03:14:20 -08:00
Emil J 75008b70e5
Merge pull request #5638 from YosysHQ/emil/linux_perf-fix-help 
linux_perf: mark internal, fix help formatting
 2026-01-28 11:06:08 +01:00
Miodrag Milanović 97366933b3
Merge pull request #5643 from YosysHQ/update_abc 
Update ABC as per 2026-01-28
 2026-01-28 10:21:08 +01:00