mirror of https://github.com/YosysHQ/yosys.git
Reorder ff.remove in opt_dff
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@ -399,7 +399,6 @@ struct OptDffWorker
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// ALOAD always active
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log("Handling always-active async load on %s (%s) from module %s (changing to combinatorial circuit).\n",
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log_id(cell), log_id(cell->type), log_id(module));
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ff.remove();
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if (ff.has_sr) {
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SigSpec tmp;
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@ -427,6 +426,7 @@ struct OptDffWorker
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} else {
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module->connect(ff.sig_q, ff.sig_ad);
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}
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ff.remove();
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return true;
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}
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