luke
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix verific issue

This commit is contained in:
Akash Levy 2026-02-01 00:16:10 -08:00
parent bdc9ad9f53
commit 7c70026610
1 changed files with 6 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
frontends/verific/verific.cc
View File

@ -3862,11 +3862,16 @@ struct VerificPass : public Pass {
if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F" || args[argidx] == "-FF"))
{
unsigned verilog_mode = veri_file::SYSTEM_VERILOG;
#ifdef YOSYSHQ_VERIFIC_EXTENSIONS
unsigned verilog_mode = veri_file::UNDEFINED;
unsigned vhdl_mode = vhdl_file::UNDEFINED;
bool is_formal = false;
#endif
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
unsigned verilog_mode = veri_file::SYSTEM_VERILOG;
#endif
#ifdef VERIFIC_VHDL_SUPPORT
unsigned vhdl_mode = vhdl_file::UNDEFINED;
#endif
const char* filename = nullptr;