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Reducing verbosity for cell printing

This commit is contained in:
AdvaySingh1 2026-01-30 13:11:36 -08:00
parent 7dab62cb42
commit fc61433faa
1 changed files with 0 additions and 1 deletions
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1
passes/techmap/abc.cc
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@ -1490,7 +1490,6 @@ void AbcModuleState::extract(AbcSigMap &assign_map, dict<SigSpec, std::string> &
for (auto c : mapped_mod->cells())
{
// SILIMATE: set output port to either Y or Q depending on the cell's ports and apply src attribute to the driver cell
log("Processing cell %s\n", c->name.c_str());
pool<string> src_pool;
if (c->hasPort(ID::Y) || c->hasPort(ID::Q)) {
Wire *out_wire = c->getPort((c->hasPort(ID::Y)) ? ID::Y : ID::Q).as_wire();