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5448 Commits

Author SHA1 Message Date
AdvaySingh1 90dbb91cae Changed min cone size 2026-02-17 16:22:05 -08:00
AdvaySingh1 2ab89e1146 Passing equiv_opt pass and speed boosts 2026-02-17 16:13:51 -08:00
AdvaySingh1 c8b6869e65 Removed optimizations from infer_ce.cc for profiling 2026-02-17 15:20:57 -08:00
AdvaySingh1 a8e4fccc56 Removed simulation and isValidGatingSignal function 2026-02-17 14:07:22 -08:00
AdvaySingh1 fa9e7a77d7 Removed normal clockgate pass options form sate_clockgate pass 2026-02-17 13:43:22 -08:00
AdvaySingh1 efcabb270f Added caching of simulation runs for speed 2026-02-17 13:38:32 -08:00
AdvaySingh1 499e83a549 Switched to using CE module. Mostly retaining SAT gates. Still needs speedup 2026-02-17 12:41:59 -08:00
AdvaySingh1 e755f6c42e Added initial simulation. Incorrect simulation -- changed the number of accedpted results as well as increasing runtime 2026-02-17 12:14:53 -08:00
AdvaySingh1 2212d85626 Changed configurations to match the OpenROAD project 2026-02-17 11:57:56 -08:00
AdvaySingh1 144db54c4e Changed to inverse hashing for more flexibility 2026-02-17 11:53:06 -08:00
AdvaySingh1 f0de3ae8de Initial sat_clockgate pass pre speed optimization 2026-02-17 11:19:18 -08:00
AdvaySingh1 cc6605f8e2 Added passing on the args into the clockgate pass so there's an icg cell for the mapping 2026-02-17 10:49:18 -08:00
AdvaySingh1 2ab34262ec Added profiling info before and after sat_clockgate pass 2026-02-17 09:23:32 -08:00
AdvaySingh1 3567960671 Changed hashing from string to pair with vector and bool 2026-02-13 17:01:58 -08:00
AdvaySingh1 5ce8aada27 Added profiling for literal count 2026-02-13 16:34:15 -08:00
AdvaySingh1 3442bc3a85 Changed indexing to be based on the literal ID in EZSat and sorted to allow better hashing 2026-02-13 16:15:31 -08:00
AdvaySingh1 80fbdf7e6a Removed duplication of vectors and called clockgate pass post creating enable signals 2026-02-13 15:33:45 -08:00
AdvaySingh1 feffbbe32c Added initial impl based on OpenROAD 2026-02-12 16:12:50 -08:00
AdvaySingh1 514c01efd2 Added prune expressions list TODO 2026-02-12 12:14:25 -08:00
AdvaySingh1 745f17a34e Changed input_set_is_enable_exact to XOR Mitter 2026-02-12 11:10:10 -08:00
AdvaySingh1 532d1d45a8 Resolved adding SigBits from Q using static EXCLUDE_Q_FROM_ENABLE knob 2026-02-11 15:08:49 -08:00
AdvaySingh1 4ca4392e9b Simplied recursion in sat_clockgate pass 2026-02-11 14:56:46 -08:00
AdvaySingh1 dd3f2e370c Fixed naming for bfs_find_potential_enable_inputs 2026-02-11 12:31:13 -08:00
AdvaySingh1 5b384511f2 Added initial SatClockgateWorker 2026-02-11 11:02:15 -08:00
AdvaySingh1 b4cd82bacf Added initial printing of the clocks with dump_flipflops_to_file 2026-02-11 10:56:07 -08:00
AdvaySingh1 6ad01fa850 Added initial pass structure 2026-02-10 14:33:37 -08:00
AdvaySingh1 b53acb0ff0 Added pass in Makefile.inc 2026-02-10 14:33:17 -08:00
AdvaySingh1 b4ef420c3f Added inital SAT based clock gating file 2026-02-10 14:02:15 -08:00
Akash Levy ee46f498e1
Update negopt.cc 2026-02-07 17:54:16 -08:00
tondapusili 6bb43f109c fixed edge cases in negopt passes, fixed cell naming inconsistencies 2026-02-06 16:38:55 -08:00
tondapusili d592f312ab mux_push implementation 2026-02-05 16:49:59 -08:00
Akash Levy 5f7658ca7c
Merge branch 'YosysHQ:main' into main 2026-02-05 13:10:34 -08:00
Emil J 1717fa0180
Merge pull request #5663 from YosysHQ/emil/opt_expr-fix-pow-shift 
opt_expr: fix const lhs of $pow to $shl
 2026-02-05 13:09:01 +01:00
Akash Levy f74ac17a5f Undo the terrible upstream changes that break everything... 2026-02-04 22:26:06 -08:00
Akash Levy d3ab45c2fa
Merge branch 'YosysHQ:main' into main 2026-02-04 15:53:43 -08:00
AdvaySingh1 8d22f6d7e1 Merged with main 2026-02-04 13:00:22 -08:00
AdvaySingh1 607ef02339 Added abc_max_node_retention_origins flag in AbcConfig struct 2026-02-04 12:12:04 -08:00
AdvaySingh1 43027720d2 Fixed no sources log error to only output error if node_retention mode is on 2026-02-04 10:22:24 -08:00
Emil J 8bbde80e02
Merge pull request #5631 from rocallahan/cleanup-compare-signals 
Clean up `compare_signals()` in `opt_clean`
 2026-02-04 17:45:05 +01:00
Emil J 992e64342c
Merge pull request #5621 from rocallahan/remove-opt-sort 
Remove `Design::sort()` calls from optimization passes
 2026-02-04 16:55:56 +01:00
Akash Levy 48e7b5a167 Let's go back to a simpler time for abc... 2026-02-04 04:33:19 -08:00
Akash Levy c57c49873e Please just stop modifying yosys... 2026-02-04 03:48:58 -08:00
Akash Levy 241852eebd Test merge from upstream 2026-02-04 02:07:01 -08:00
Akash Levy af7e124c26
Merge pull request #101 from Silimate/yosys_abc_test1 
Small abc update to see what happens
 2026-02-04 01:45:56 -08:00
Akash Levy dd08ba75bc
Merge pull request #100 from Silimate/negopt-pass-pr 
Add negopt pass with comprehensive pattern matching
 2026-02-04 01:44:45 -08:00
Akash Levy 715e062bcd Merge branch 'main' into negopt-pass-pr 2026-02-04 00:15:53 -08:00
Akash Levy 0e0740a3a0
Remove unnecessary blank line in abc.cc 2026-02-04 00:08:42 -08:00
Akash Levy 33bcfe26dd Merge branch 'main' into sim 2026-02-03 23:57:24 -08:00
Akash Levy 23ed2ef523 Small abc update to see what happens 2026-02-03 23:55:25 -08:00
Akash Levy 807df40422 Undo the weird abc changes 2026-02-03 23:21:48 -08:00