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16,017 Commits 131 Branches 66 Tags 62 MiB
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16017 Commits

Author SHA1 Message Date
Emil J. Tywoniak 8d585b1387 rtlil_bufnorm: more xlog 2026-04-09 13:17:49 +02:00
Emil J. Tywoniak a287c24e75 design: properly switch signorm mode when restoring saved designs 2026-04-09 13:16:37 +02:00
Emil J. Tywoniak 98c7078984 equiv_make: don't copy $input_port 2026-04-08 11:40:19 +02:00
Emil J. Tywoniak 8ab4e03244 rtlil: fix cloneInto in signorm 2026-04-08 11:39:24 +02:00
Emil J. Tywoniak 8831f3245d rtlil: sigNormalize Module when added to Design in signorm mode 2026-04-07 20:05:51 +02:00
Emil J. Tywoniak b6ca1beabc read_verilog: remove log I left behind by accident 2026-04-07 19:52:46 +02:00
Emil J. Tywoniak 8798b15fa0 rtlil_bufnorm: more xlog 2026-04-07 19:30:19 +02:00
Emil J. Tywoniak 42e01aa1ca intel: register bram celltypes 2026-04-02 17:01:32 +02:00
Emil J. Tywoniak 0351f852cc rtlil_bufnorm: ignore timing info harder 2026-04-02 17:01:09 +02:00
Emil J. Tywoniak 07f5307bd4 gowin: replace positional arguments in cells_sim.v with named 2026-04-02 13:00:02 +02:00
Emil J. Tywoniak c7e56da381 Revert "techmap: call hierarchy on map files to determine port directions" 
This reverts commit eabbf6d225.
 2026-04-02 11:40:33 +02:00
Emil J. Tywoniak e66b9b48aa fixup! timinginfo: special-case $specify2 in signorm invariant 2026-04-01 16:55:40 +02:00
Emil J. Tywoniak 956e5d6de9 gowin: LUT count rebless 2026-04-01 13:15:47 +02:00
Emil J. Tywoniak 8bc1aac882 hierarchy: tolerance for apparent recursive instances in techmap files 2026-04-01 13:12:41 +02:00
Emil J. Tywoniak eabbf6d225 techmap: call hierarchy on map files to determine port directions 2026-04-01 12:46:31 +02:00
Emil J. Tywoniak bc7de102cd tests: use memory -bram-register in tests/bram 2026-03-31 15:00:26 +02:00
Emil J. Tywoniak 9f5a95469d memory: add -bram-register 2026-03-31 14:59:59 +02:00
Emil J. Tywoniak 0f3efd2c1a fixup! memory_bram: add -register 2026-03-31 14:59:34 +02:00
Emil J. Tywoniak 4fcd50ed7a memory_bram: add -register 2026-03-31 14:59:10 +02:00
Robert O'Callahan 087ebdd6e4 Move `Design::sort()` calls out of `opt` and `opt_clean` passes into the synth passes that need them. 2026-03-27 15:16:08 +01:00
Emil J. Tywoniak b1457934ab sort: init 2026-03-27 15:13:47 +01:00
Emil J. Tywoniak c6923ed2a7 ffmerge: initvals signorm compatibility fixup 2026-03-26 23:53:53 +01:00
Emil J. Tywoniak c06755f1bb timinginfo: special-case $specify2 in signorm invariant 2026-03-26 19:42:33 +01:00
Emil J. Tywoniak d33d048874 fixup! opt_expr: with -keepdc disable equality optimization rules that break when ports are sigmapped 2026-03-25 12:39:33 +01:00
Emil J. Tywoniak e3edd1501e modtools: fix port_del db erase 2026-03-25 12:17:23 +01:00
Emil J. Tywoniak 1775bce173 opt_expr: with -keepdc disable equality optimization rules that break when ports are sigmapped 2026-03-25 11:50:17 +01:00
Emil J. Tywoniak c416d39ebb techmap: read_verilog -icells, I mean, obviously 2026-03-24 23:25:42 +01:00
Emil J. Tywoniak 09040adb2c connect: remove input ports on conflict 2026-03-24 23:23:27 +01:00
Emil J. Tywoniak 15665773fd opt_dff: sigma harder, FfDataSigMapped 2026-03-24 23:22:39 +01:00
Emil J. Tywoniak 1fb904e281 ff: add FfDataSigMapped 2026-03-24 23:22:39 +01:00
Emil J. Tywoniak 734249a5e6 opt_dff: temporarily disable signorm due to muxtree traversal 2026-03-24 23:22:39 +01:00
Emil J. Tywoniak 49d08591e3 tests: fix rtlil roundtrip test 2026-03-24 23:22:39 +01:00
Emil J. Tywoniak 872c940259 design: fix signorm commit connectivity to design 2026-03-18 00:44:20 +01:00
Emil J. Tywoniak a4398d4d90 fixup! cxxrtl: ignore $input_port 2026-03-17 23:00:22 +01:00
Emil J. Tywoniak b97a8cdfe3 cxxrtl: ignore $input_port 2026-03-17 18:06:07 +01:00
Emil J. Tywoniak 55189bc65c flatten: redo signormalization to work around fanout issue 2026-03-17 18:04:41 +01:00
Emil J. Tywoniak 4c8b7818f4 abstract: fix test signorm 2026-03-17 17:39:05 +01:00
Emil J. Tywoniak c01d88c303 signorm: disable passes that use rewrite_sigspecs 2026-03-17 17:35:57 +01:00
Emil J. Tywoniak 961c9a90d6 aiger: ignore $input_port 2026-03-17 17:32:56 +01:00
Emil J. Tywoniak c5d4b435bd check: stitch info about $connect ports together for driver analysis 2026-03-17 17:29:23 +01:00
Emil J. Tywoniak bbf5b3c738 signorm: remove $input cells when leaving 2026-03-17 16:37:00 +01:00
Emil J. Tywoniak 3257b8ae1e abstract: skip $input_port cells 2026-03-17 16:34:41 +01:00
Emil J. Tywoniak 9d3928c014 flatten: skip $input_port cells in template module 2026-03-17 16:11:32 +01:00
Emil J. Tywoniak debc2c3977 signorm: skip const when fixing fanout 2026-03-17 11:28:10 +01:00
Emil J. Tywoniak 869a7303b0 signorm: disable in passes that use swap_names 2026-03-16 22:45:29 +01:00
Emil J. Tywoniak 3502a51598 opt_expr: fix invert_map 2026-03-13 12:18:48 +01:00
Emil J. Tywoniak aee094e3c4 fixup! fixup! satgen: support $connect 2026-03-12 22:53:31 +01:00
Emil J. Tywoniak 4d1f8fd7d3 fixup! satgen: support $connect 2026-03-12 22:16:06 +01:00
Emil J. Tywoniak 0d353591fe satgen: support $connect 2026-03-12 22:15:34 +01:00
Emil J. Tywoniak ae946a598c rtlil: add dump_sigmap for hacky signorm debugging 2026-03-12 22:13:21 +01:00