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fixup! timinginfo: special-case $specify2 in signorm invariant
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@ -1057,7 +1057,7 @@ void RTLIL::Cell::unsetPort(const RTLIL::IdString& portname)
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void RTLIL::Cell::setPort(const RTLIL::IdString& portname, RTLIL::SigSpec signal)
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{
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bool is_input_port = false;
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if (module->sig_norm_index != nullptr && type != ID($specify2)) {
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if (module->sig_norm_index != nullptr && type != ID($specify2) && type != ID($specify3) && type != ID($specrule)) {
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module->sig_norm_index->sigmap.apply(signal);
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auto dir = port_dir(portname);
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