mirror of https://github.com/YosysHQ/yosys.git
equiv_make: don't copy $input_port
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8ab4e03244
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98c7078984
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@ -114,6 +114,8 @@ struct EquivMakeWorker
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if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
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cell_names.insert(it->name);
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gold_clone->rename(it, it->name.str() + "_gold");
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if (it->type == ID($input_port))
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gold_clone->remove(it);
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}
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for (auto it : gate_clone->wires().to_vector()) {
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@ -126,6 +128,8 @@ struct EquivMakeWorker
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if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
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cell_names.insert(it->name);
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gate_clone->rename(it, it->name.str() + "_gate");
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if (it->type == ID($input_port))
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gate_clone->remove(it);
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}
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gold_clone->cloneInto(equiv_mod);
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@ -513,6 +517,7 @@ struct EquivMakePass : public Pass {
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worker.equiv_mod = design->addModule(RTLIL::escape_id(args[argidx+2]));
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worker.run();
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Pass::call(design, "dump");
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}
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} EquivMakePass;
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