mirror of https://github.com/YosysHQ/yosys.git
modtools: fix port_del db erase
This commit is contained in:
parent
1775bce173
commit
e3edd1501e
|
|
@ -110,8 +110,11 @@ struct ModIndex : public RTLIL::Monitor
|
|||
{
|
||||
for (int i = 0; i < GetSize(sig); i++) {
|
||||
RTLIL::SigBit bit = sigmap(sig[i]);
|
||||
if (bit.wire)
|
||||
if (bit.wire) {
|
||||
database[bit].ports.erase(PortInfo(cell, port, i));
|
||||
if (!database[bit].is_input && !database[bit].is_output && database[bit].ports.empty())
|
||||
database.erase(bit);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue