mirror of https://github.com/YosysHQ/yosys.git
rtlil: add dump_sigmap for hacky signorm debugging
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@ -1753,6 +1753,7 @@ public:
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pool<RTLIL::Cell *> pending_deleted_cells;
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dict<RTLIL::Wire *, pool<RTLIL::Cell *>> buf_norm_connect_index;
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void bufNormalize();
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void dump_sigmap();
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protected:
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SigNormIndex *sig_norm_index = nullptr;
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@ -55,6 +55,19 @@ struct RTLIL::SigNormIndex
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setup_fanout();
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}
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void dump_sigmap() {
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for (auto [name, wire] : module->wires_) {
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log_debug("wire %s %p %s\n", name, wire, wire->name);
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SigSpec ss(wire);
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log_debug("ss %s\n", log_signal(ss));
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sigmap(ss);
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log_debug("sigmapped %s\n", log_signal(ss));
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}
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for (auto [lhs, rhs] : module->connections_) {
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log_debug("connection %s %s\n", log_signal(lhs), log_signal(rhs));
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}
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}
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void normalize() {
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flush_connections();
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flush_newly_driven();
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@ -345,6 +358,12 @@ void RTLIL::Module::sigNormalize()
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}
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void RTLIL::Module::dump_sigmap()
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{
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if (sig_norm_index != nullptr)
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sig_norm_index->dump_sigmap();
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}
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void RTLIL::Module::clear_sig_norm_index()
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{
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if (sig_norm_index == nullptr)
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